Re: [PATCH/RFC] MTD: Striping layer core

[Alexander Belyakov <alexander.belyakov@intel.com>]

Artem B. Bityutskiy wrote:
> Well, probably this is a perversion and is not needed in reality, but
> still. I conceive it like this. Yo have 2 flashes. You as usually,
> calculate the resulting eraseblock size. You see at the minimal I/O unit
> size of both flashes and similarly calculate the resulting minimal I/O
> size. So that's it. You'll end up with a though perverted, but still a
> striped MTD device.

First problem in case of striping NOR and NAND is a question about type 
of striped device. Should we report it as NOR or as NAND. I believe it 
is important for clients to know about that. Imagine, for example, 
device reported as NAND behaves as NOR or vice versa. Another problem is 
a difference in operation speed. Apparently you won't get any 
performance gain. These are only top of iceberg. Note that even plain 
and simple mtdconcat is not supposed to work with flashes of different 
types.

Alexander Belyakov