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From: Vitaly Wool <vwool@ru.mvista.com>
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Cc: Alexander Belyakov <alexander.belyakov@intel.com>, "Kutergin,
	Timofey" <timofey.kutergin@intel.com>, "Korolev,
	Alexey" <alexey.korolev@intel.com>, linux-mtd@lists.infradead.org,
	"Artem B. Bityutskiy" <dedekind@yandex.ru>, Nicolas Pitre <nico@cam.org>
Subject: Re: [PATCH/RFC] MTD: Striping layer core
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Thomas Gleixner wrote:
> Functions like concat or striping can only be used with FLASH of the
> same type. NAND and NOR are so fundamentally different it wont work
> without some ugly hack around. There is no point to even think about
> that.
>   
I'm afraid I can't object against that ;)
> Also striping on NAND is a seperate topic. Most new hardware designs
> have NAND controllers included which provide e.g. hardware based ECC.
> Most of the controllers I'm aware of are not really suitable for
> striping due to their design. Also striping would require a fundamental
> change to the NAND code, as it currently serializes the access to shared
> hardware controllers. This seralization needs to be carefully redesigned
> to allow striping and even then it depends on the controller and the
> overall hardware design (most designs have OR-wired ready/busy pins)
> whether it's possible or not.
>
>   
Given that some modern NAND controllers have the ability to generate 
interrupt when they're done, I would think about complete redesign of 
the MTD NAND layer. I'd like to see the fully asynchronous base model 
here (i. e. mtd->send_write_cmd/send_read_cmd or something similar) and 
synchronous interface on top of that, just like, say, the current SPI 
core works.
This would allow to be more flexible in waiting for completion and also 
would IMO make striping implementation for NAND more straightforward. 
Does that make sense?

Vitaly