Re: [PATCH/RFC] MTD: Striping layer core

[Alexander Belyakov <alexander.belyakov@intel.com>]

Thomas Gleixner wrote:
>> Oh really? What about MP3 player-oriented design with NAND flash as a
>> main storage and NOR flash for kernel/userspace XIP etc?
>
> Granted, but you can not mix the usage of those chips.
>
> Functions like concat or striping can only be used with FLASH of the
> same type. NAND and NOR are so fundamentally different it wont work
> without some ugly hack around. There is no point to even think about
> that.

That's my point too. Moreover there is no reason to stripe NOR and NAND. 
Even if you were able to make "some ugly hacks" to configure it you wont 
get any performance increase due to significantly different speed of 
those chips. Striped device will work with the speed of the slowest 
sub-device.

> I have the feeling that the striping support
> needs more than a bunch of hacks to the core mtd chip support if we do
> not want to end up with a complete unmaintainable mess.

Originally striping layer has been developed for NOR and Sibley flashes 
which quite slow. Striping for NOR is quite simple despite it requires 
some changes in command sets implementation.

If you look at my patches you find nothing that changes MTD NAND 
subsystem. Only interleaving algorithm (virtual pages merging) and 
worker threads queues have been implemented for NAND flashes. It was not 
possible to check striped NAND performance gain due to some hardware 
limitations we have - but I believe NAND striping will come across the 
same problems with thread switching as we had for NOR devices. Anyway I 
feel that in general NAND striping wont be so simple as NOR striping.

Thanks,
Alexander