--- drivers/mtd.old/nand/at91_nand.c	2006-06-20 09:09:21.000000000 +0200
+++ drivers/mtd/nand/at91_nand.c	2006-06-20 09:33:21.000000000 +0200
@@ -39,12 +39,13 @@
 /*
  * Hardware specific access to control-lines
  */
-static void at91_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
 	struct nand_chip *nand_chip = mtd->priv;
 	struct at91_nand_host *host = nand_chip->priv;
 
-	switch(cmd) {
+	if (ctrl & NAND_CTRL_CHANGE) {
+		switch(cmd) {
 		case NAND_CTL_SETCLE:
 			nand_chip->IO_ADDR_W = host->io_base + (1 << host->board->cle);
 			break;
@@ -61,7 +62,10 @@
 			break;
 		case NAND_CTL_CLRNCE:
 			break;
+		}
 	}
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, chip->IO_ADDR_W);
 }
 
 
@@ -145,13 +149,14 @@
 
 	nand_chip->priv = host;		/* link the private data structures */
 	mtd->priv = nand_chip;
+	mtd->owner = THIS_MODULE;
 
 	/* Set address of NAND IO lines */
 	nand_chip->IO_ADDR_R = host->io_base;
 	nand_chip->IO_ADDR_W = host->io_base;
-	nand_chip->hwcontrol = at91_nand_hwcontrol;
+	nand_chip->cmd_ctrl = at91_nand_hwcontrol;
 	nand_chip->dev_ready = at91_nand_device_ready;
-	nand_chip->eccmode = NAND_ECC_SOFT;	/* enable ECC */
+	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
 	nand_chip->chip_delay = 20;		/* 20us command delay time */
 
 	platform_set_drvdata(pdev, host);
@@ -170,6 +175,7 @@
 		res = -ENXIO;
 		goto out;
 	}
+	nand_release(mtd);
 
 #ifdef CONFIG_MTD_PARTITIONS
 	if (host->board->partition_info)