about using UBI on MLC Nand flash

about using UBI on MLC Nand flash

[Marteo Tim]

I noticed that UBI need to write 2 times at 1st page in 1 block, one
for EC header, and the other for VID header. But it is not suitable
for MLC NAND flash, which only can write once per page. And by
default, MTD's nand_write can only write page-aligned data.
Although we can set the module parameter vid_hdr_offsets to the 2nd
page, but it will occupy more flash space. It is in a dilemma. :(

marteo

Re: about using UBI on MLC Nand flash

[Artem B. Bityutskiy]

Hello Tim,

Marteo Tim wrote:
> I noticed that UBI need to write 2 times at 1st page in 1 block, one
> for EC header, and the other for VID header. But it is not suitable
> for MLC NAND flash, which only can write once per page. And by
> default, MTD's nand_write can only write page-aligned data.
> Although we can set the module parameter vid_hdr_offsets to the 2nd
> page, but it will occupy more flash space. It is in a dilemma. :(

I wonder, what's your flash What's the NAND page size of your flash?

unfortunately, I failed to find any MLC NAND flash manual to read about
it. If you could send me one, I'd be grateful. Or URL? Is it only
Toshiba who produce them?

Is this a feature of MLC NANDs or this is just MTD which does not
support multiple writes? For example, Samsung SLC flashes *do* support 4
writes per NAND page, but MTD *does not* support this so far (but there
is a plan to implement this).

And it is strange if UBI tries to write to one NAND page twice at your
case. By default it should not, granted mtd->writesize is correct in
your case.

I guess you read at UBI-FAQ? FYI:

-------------------
"How much flash space do UBI headers consume?

This depends on the flash flash you are using. Both EC and VID headers
take 64 bytes, so in case of NOR flash UBI headers consume 128 bytes,
and the logical eraseblock size is equivalent to the physical eraseblock
size minus 128 bytes. But the situation may be different in case of
other flash types.

As it is noted here , UBI writes twice to the flash, not just both UBI
headers in one go. But many flashes have a notion of the "minimal
Input/Output unit size". For example, in case of NAND flash it is
typically equivalent to the NAND page size, which is either 512 bytes or
2KiB. In this case, the EC header would be situated at the first NAND
page, the VID header - at the second NAND page, and both headers would
take two NAND pages (1KiB or 4KiB). The situation is similar in case of
other flash types.

Implementation-wise, UBI just looks at the writesize field of the struct
mtd_info MTD device description object and uses it as the min. I/O unit
when calculating sizes and positions of UBI headers.

Fortunately, many NAND flashes allow several (typically 4) write
operations to one NAND page. Thus, say, in case of a Samsung flash with
2KiB NAND pages one may fit UBI headers at the first two 512-byte chunks
of the NAND page. But this must be supported by the MTD flash driver
(writesize has to be 512 bytes, not 2KiB)."
-------------------

-- 
Best Regards,
Artem B. Bityutskiy,
St.-Petersburg, Russia.

Re: about using UBI on MLC Nand flash

[Marteo Tim]

2006/7/28, Artem B. Bityutskiy <dedekind@yandex.ru>:
> Hello Tim,
>
> Marteo Tim wrote:
> > I noticed that UBI need to write 2 times at 1st page in 1 block, one
> > for EC header, and the other for VID header. But it is not suitable
> > for MLC NAND flash, which only can write once per page. And by
> > default, MTD's nand_write can only write page-aligned data.
> > Although we can set the module parameter vid_hdr_offsets to the 2nd
> > page, but it will occupy more flash space. It is in a dilemma. :(
>
> I wonder, what's your flash What's the NAND page size of your flash?
>

My NAND flash page size is 2k byte.

> unfortunately, I failed to find any MLC NAND flash manual to read about
> it. If you could send me one, I'd be grateful. Or URL? Is it only
> Toshiba who produce them?
>

OK, I'm glad to send it to you, include SAMSUNG&TOSHIBA's MLC NAND
flash datasheet, please check your email, :)

> Is this a feature of MLC NANDs or this is just MTD which does not
> support multiple writes? For example, Samsung SLC flashes *do* support 4
> writes per NAND page, but MTD *does not* support this so far (but there
> is a plan to implement this).
>

By now, as the datasheet described, MLC NAND flash cannot write exceed
one time for main area and one time for spare area. I don't know it is
due to manufacture technology's limit or other reasons.

> And it is strange if UBI tries to write to one NAND page twice at your
> case. By default it should not, granted mtd->writesize is correct in
> your case.
>

Yes, for SLC NAND flash, it would be easy to write more times per page
by setting mtd->writesize to 512.

Due to cheap price, MLC NAND flash maybe use more and more popular,
especially in bulky flash. Yaffs2 can already support MLC chips by
zero page rewrites, and I want UBI can support it too. :)

Re: about using UBI on MLC Nand flash

[Vitaly Wool]

Marteo Tim wrote:
> Due to cheap price, MLC NAND flash maybe use more and more popular,
> especially in bulky flash. Yaffs2 can already support MLC chips by
> zero page rewrites, and I want UBI can support it too. :)
>   
Absolutely, and also it'd be nice to see JFFS2 being MLC-ready, as 
opposed to its current status...

Vitaly

Re: about using UBI on MLC Nand flash

[Artem B. Bityutskiy]

Marteo Tim wrote:
> OK, I'm glad to send it to you, include SAMSUNG&TOSHIBA's MLC NAND
> flash datasheet, please check your email, :)
Thanks!

> Due to cheap price, MLC NAND flash maybe use more and more popular,
> especially in bulky flash. Yaffs2 can already support MLC chips by
> zero page rewrites, and I want UBI can support it too. :)

Well, UBI works in this case as well. But it anyway needs 2 write 
operations. So, in your case, we'll spend 4K for UBI headers in each 
eraseblock... It's wastful, agree, but may be appropriate in some 
applications.

-- 
Best Regards,
Artem B. Bityutskiy,
St.-Petersburg, Russia.