From: Eugene <eugene.kozlov@promwad.com>
To: linux-mtd@lists.infradead.org
Subject: nand_base questions
Date: Fri, 19 Jan 2007 18:52:33 +0000 [thread overview]
Message-ID: <45B11371.2080400@promwad.com> (raw)
Hello i just confused because:
1. NAND_CMD_STATUS command realized in NAND_CMD_RESET case:
case NAND_CMD_RESET:
if (this->dev_ready)
break;
udelay(this->chip_delay);
this->hwcontrol(mtd, NAND_CTL_SETCLE);
this->write_byte(mtd, NAND_CMD_STATUS);
this->hwcontrol(mtd, NAND_CTL_CLRCLE);
while ( !(this->read_byte(mtd) & NAND_STATUS_READY));
return;
2. One time uses
if (!this->dev_ready) {
udelay (this->chip_delay);
return;
another
if (!this->dev_ready)
udelay (this->chip_delay);
else
nand_wait_ready(mtd);
another
if (this->dev_ready) {
if (this->dev_ready(mtd))
break;
} else {
if (this->read_byte(mtd) & NAND_STATUS_READY)
break;
What the conception? Because as i understand read status register isn't
working yet.
reply other threads:[~2007-01-19 16:54 UTC|newest]
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