* How to map nand chip ?
@ 2007-11-13 19:26 Carlos Munoz
2007-11-15 19:25 ` Carlos Munoz
0 siblings, 1 reply; 5+ messages in thread
From: Carlos Munoz @ 2007-11-13 19:26 UTC (permalink / raw)
To: linux-mtd
I'm working on a custom board that has both nor and nand flash. I mapped
the nor flash (cfi) using do_map_probe("cfi_probe", &map). However, I'm
not sure what argument to pass to do_map_probe() to map the nand flash.
Does anyone know how nand flash is mapped or point me to the right
documents ?
Thanks,
Carlos
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: How to map nand chip ?
2007-11-13 19:26 How to map nand chip ? Carlos Munoz
@ 2007-11-15 19:25 ` Carlos Munoz
2007-11-15 21:44 ` Ricard Wanderlof
0 siblings, 1 reply; 5+ messages in thread
From: Carlos Munoz @ 2007-11-15 19:25 UTC (permalink / raw)
To: linux-mtd; +Cc: Carlos Munoz
Carlos Munoz wrote:
> I'm working on a custom board that has both nor and nand flash. I mapped
> the nor flash (cfi) using do_map_probe("cfi_probe", &map). However, I'm
> not sure what argument to pass to do_map_probe() to map the nand flash.
>
> Does anyone know how nand flash is mapped or point me to the right
> documents ?
>
OK. I figured it out... had to write a board nand driver.
When I load the nand driver module, the nand chip is detected correctly
but it seems all the erase blocks are bad. I wonder if it's caused by
the wrong timings when accessing the nand chip. However, the
manufacturer and chip id are read correctly. Does anyone know what may
be the cause for these errors ?
The output is as follows:
modprobe migo_r
NAND device: Manufacturer ID: 0xec, Chip ID: 0xd3 (Samsung NAND 1GiB
3,3V 8-bit)
Scanning device for bad blocks
Bad eraseblock 1 at 0x00020000
Bad eraseblock 2 at 0x00040000
Bad eraseblock 3 at 0x00060000
Bad eraseblock 4 at 0x00080000
Bad eraseblock 5 at 0x000a0000
Bad eraseblock 6 at 0x000c0000
Bad eraseblock 7 at 0x000e0000
Bad eraseblock 8 at 0x00100000
Bad eraseblock 9 at 0x00120000
Bad eraseblock 10 at 0x00140000
....
Thanks,
Carlos
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: How to map nand chip ?
2007-11-15 19:25 ` Carlos Munoz
@ 2007-11-15 21:44 ` Ricard Wanderlof
2007-11-16 10:41 ` Carl-Daniel Hailfinger
2007-11-20 23:50 ` Carlos Munoz
0 siblings, 2 replies; 5+ messages in thread
From: Ricard Wanderlof @ 2007-11-15 21:44 UTC (permalink / raw)
To: Linux mtd
On Thu, 15 Nov 2007, Carlos Munoz wrote:
> When I load the nand driver module, the nand chip is detected correctly
> but it seems all the erase blocks are bad. I wonder if it's caused by
> the wrong timings when accessing the nand chip. However, the
> manufacturer and chip id are read correctly. Does anyone know what may
> be the cause for these errors ?
The timing requirements when reading chip id's are not as severe as when
actually accessing the memory, so if you are just below the limit, you can
get the id ok but other things fail.
Another thing that can cause this is if the ready/busy-pin is not read
properly by the chip driver. Again, the chip will probably respond quickly
to an id request, but when reading or writing the memory array, the access
times will be longer causing failure.
/Ricard
--
Ricard Wolf Wanderlöf ricardw(at)axis.com
Axis Communications AB, Lund, Sweden www.axis.com
Phone +46 46 272 2016 Fax +46 46 13 61 30
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: How to map nand chip ?
2007-11-15 21:44 ` Ricard Wanderlof
@ 2007-11-16 10:41 ` Carl-Daniel Hailfinger
2007-11-20 23:50 ` Carlos Munoz
1 sibling, 0 replies; 5+ messages in thread
From: Carl-Daniel Hailfinger @ 2007-11-16 10:41 UTC (permalink / raw)
To: Ricard Wanderlof; +Cc: Linux mtd
On 15.11.2007 22:44, Ricard Wanderlof wrote:
> On Thu, 15 Nov 2007, Carlos Munoz wrote:
>
>
>> When I load the nand driver module, the nand chip is detected correctly
>> but it seems all the erase blocks are bad. I wonder if it's caused by
>> the wrong timings when accessing the nand chip. However, the
>> manufacturer and chip id are read correctly. Does anyone know what may
>> be the cause for these errors ?
>>
>
> The timing requirements when reading chip id's are not as severe as when
> actually accessing the memory, so if you are just below the limit, you can
> get the id ok but other things fail.
Side note: I have seen very old chips (from 1999, don't remember whether
they were NAD though) where reading chip IDs needed longer timing than
reading memory, but that is not the case here.
Regards,
Carl-Daniel
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: How to map nand chip ?
2007-11-15 21:44 ` Ricard Wanderlof
2007-11-16 10:41 ` Carl-Daniel Hailfinger
@ 2007-11-20 23:50 ` Carlos Munoz
1 sibling, 0 replies; 5+ messages in thread
From: Carlos Munoz @ 2007-11-20 23:50 UTC (permalink / raw)
To: Ricard Wanderlof; +Cc: Linux mtd
Ricard Wanderlof wrote:
> Another thing that can cause this is if the ready/busy-pin is not read
> properly by the chip driver. Again, the chip will probably respond quickly
> to an id request, but when reading or writing the memory array, the access
> times will be longer causing failure.
>
>
That was the problem. The ready/busy pin was not working. Somehow, it's
always high.
For now I added a 20 usec delay and everything works.
Thanks,
Carlos
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2007-11-20 23:48 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2007-11-13 19:26 How to map nand chip ? Carlos Munoz
2007-11-15 19:25 ` Carlos Munoz
2007-11-15 21:44 ` Ricard Wanderlof
2007-11-16 10:41 ` Carl-Daniel Hailfinger
2007-11-20 23:50 ` Carlos Munoz
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