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* Request for testing: AMD/Fujitsu flash chips
@ 2007-11-30 17:26 David Woodhouse
  2007-12-10  7:43 ` Mike Rapoport
  0 siblings, 1 reply; 4+ messages in thread
From: David Woodhouse @ 2007-11-30 17:26 UTC (permalink / raw)
  To: linux-mtd

For a long time, there's been confusion about the "unlock addresses" for
AMD-compatible NOR flash -- the chip definition in our table have an
_array_ giving the addresses at which we should do the magic unlock
write cycles, according to the different modes (16-bit, 8-bit) that the
chip could be used in.

For a while now, we've been deliberately ignoring all but the first
entry in that array, on the basis that it shouldn't actually vary -- the
chip needs the same levels on the same address lines, whatever mode it's
in. The data sheets can be very confusing... for example:

	5. The system should generate the following address patterns:
	    Word Mode: 555H or 2AAH to addresses A0 to A10
	    Byte Mode: AAAH or 555H to addresses A-1 to A10

I've just got rid of the array of unlock addresses, and _attempted_ to
make the code cope and work again. I would very much appreciate some
testing, before I put that in the MTD git tree:

	git://git.infradead.org/~dwmw2/jedec-unlock.git
	http://git.infradead.org/?p=users/dwmw2/jedec-unlock.git

-- 
dwmw2

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2007-12-10 15:11 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-11-30 17:26 Request for testing: AMD/Fujitsu flash chips David Woodhouse
2007-12-10  7:43 ` Mike Rapoport
2007-12-10 13:32   ` David Woodhouse
2007-12-10 15:09     ` Mike Rapoport

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