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* Question on how NAND flash BBT is stored in the chip
@ 2008-10-16 14:35 Rutger Hofman
       [not found] ` <7ccead5b0810170027h677520dav1ea09079175b93fe@mail.gmail.com>
  0 siblings, 1 reply; 2+ messages in thread
From: Rutger Hofman @ 2008-10-16 14:35 UTC (permalink / raw)
  To: linux-mtd

Good afternoon list,

I have a question how the BBT (bad block table) is stored in MTD NAND 
devices. I googled for a while, and browsed the code, but I am still not 
sure.

The question:
Is the BBT stored/retrieved using a spare layout? Is ECC 
generation/correction done for it?

This question derives from the question above: is the BBT marker pattern 
stored within a spare layout (with slots for ECC, bad block markers 
etc)? Or is it written verbatim (raw and unmangled) into the spare area?

If no ECC is used for the BBT, is that for a reason?

Thanks for the information,

Rutger Hofman
VU Amsterdam

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: Question on how NAND flash BBT is stored in the chip
       [not found] ` <7ccead5b0810170027h677520dav1ea09079175b93fe@mail.gmail.com>
@ 2008-10-17 11:30   ` Rutger Hofman
  0 siblings, 0 replies; 2+ messages in thread
From: Rutger Hofman @ 2008-10-17 11:30 UTC (permalink / raw)
  To: linux-mtd; +Cc: Du Zhongdong

Du Zhongdong wrote:
> 
> On Thu, Oct 16, 2008 at 10:35 PM, Rutger Hofman <rutger@cs.vu.nl 
> <mailto:rutger@cs.vu.nl>> wrote:
> 
>     Good afternoon list,
> 
>     I have a question how the BBT (bad block table) is stored in MTD NAND
>     devices. I googled for a while, and browsed the code, but I am still not
>     sure.
> 
>     The question:
>     Is the BBT stored/retrieved using a spare layout? Is ECC
>     generation/correction done for it?
> 
> I'm not quite sure about what you mean by "using a spare layout",  but I 
> think bbt is stored in the main area of the specific page(the member 
> "int pages[NAND_MAX_CHIPS" in struct nand_bbt_descr). 

With 'spare layout' I mean the thingy that does auto-placement etc, and 
wraps up ECC, bad block mark(s), and user data into the spare area.

> the function scan_write_bbt calls mtd->write_oob with struct 
> mtd_oob_ops.mode = MTD_OOB_PLACE, tracking down this procedure I think 
> the oob data does not change its layout when written to NAND flash.
> 
> hope this information might be of some help to you :)
> 
> 
> 
>     This question derives from the question above: is the BBT marker pattern
>     stored within a spare layout (with slots for ECC, bad block markers
>     etc)? Or is it written verbatim (raw and unmangled) into the spare area?

Thanks. When browsing the code, I thought as much, but I couldn't 
absolutely make sure whether the spare is mangled or not.

So this leaves the question: the BBT itself doesn't seem to use ECC. Is 
there a reason why not? Wouldn't it be better if it does?

Thanks,

Rutger Hofman
VU Amsterdam

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2008-10-16 14:35 Question on how NAND flash BBT is stored in the chip Rutger Hofman
     [not found] ` <7ccead5b0810170027h677520dav1ea09079175b93fe@mail.gmail.com>
2008-10-17 11:30   ` Rutger Hofman

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