bus access for NAND parts

bus access for NAND parts

[Cliff Brake]

I've been looking at interfacing a raw NAND device to a PXA270 and
have the following questions.  It seems that most devices simply use a
chip select for CE.  What is the mechanism that prevents the NAND
driver from getting pre-empted and another device access toggling the
read/write stobes and messing up the NAND cycle while the NAND chip
select is still low?  I see memory barriers that should prevent out of
order issues, but I've not located any mechanism yet for preventing a
separate device access from interfering with the NAND access.

Thanks,
Cliff

-- 
=======================
Cliff Brake
http://bec-systems.com

Re: bus access for NAND parts

[Cliff Brake]

On Wed, Oct 29, 2008 at 7:54 AM, Cliff Brake <cliff.brake@gmail.com> wrote:
> I've been looking at interfacing a raw NAND device to a PXA270 and
> have the following questions.  It seems that most devices simply use a
> chip select for CE.  What is the mechanism that prevents the NAND
> driver from getting pre-empted and another device access toggling the
> read/write stobes and messing up the NAND cycle while the NAND chip
> select is still low?  I see memory barriers that should prevent out of
> order issues, but I've not located any mechanism yet for preventing a
> separate device access from interfering with the NAND access.

Correction -- above should say:  "It seems that most devices simply use a
_GPIO_ for CE".  The chip select is set low in software, and then
multiple bus cycles are run to execute the address and data phases of
the NAND operation.  So what keeps another process from interrupting
this and running a bus cycle while the GPIO for NAND CE is still low
-- which would toggle the strobes to the NAND cs.

Thanks,
Cliff

-- 
=======================
Cliff Brake
http://bec-systems.com

Re: bus access for NAND parts

[Ricard Wanderlof]

On Thu, 30 Oct 2008, Cliff Brake wrote:

> Correction -- above should say:  "It seems that most devices simply use a
> _GPIO_ for CE".  The chip select is set low in software, and then
> multiple bus cycles are run to execute the address and data phases of
> the NAND operation.  So what keeps another process from interrupting
> this and running a bus cycle while the GPIO for NAND CE is still low
> -- which would toggle the strobes to the NAND cs.

I don't know in general, but in several systems that have multiple buses, 
the NAND flash can be the only device on a particular bus, so conflicts 
with other devices are not an issue in those cases. Otherwise, it would be 
as you say, I agree.

/Ricard
--
Ricard Wolf Wanderlöf                           ricardw(at)axis.com
Axis Communications AB, Lund, Sweden            www.axis.com
Phone +46 46 272 2016                           Fax +46 46 13 61 30

Re: bus access for NAND parts

[Matthieu CASTET]

Ricard Wanderlof a écrit :
> On Thu, 30 Oct 2008, Cliff Brake wrote:
> 
>> Correction -- above should say:  "It seems that most devices simply use a
>> _GPIO_ for CE".  The chip select is set low in software, and then
>> multiple bus cycles are run to execute the address and data phases of
>> the NAND operation.  So what keeps another process from interrupting
>> this and running a bus cycle while the GPIO for NAND CE is still low
>> -- which would toggle the strobes to the NAND cs.
> 
> I don't know in general, but in several systems that have multiple buses, 
> the NAND flash can be the only device on a particular bus, so conflicts 
> with other devices are not an issue in those cases. Otherwise, it would be 
> as you say, I agree.
> 
The s3c2412 where the nand bus is shared with SDRAM. nCE is like a gpio
set by software. But it isn't a problem because the nand flash doesn't
care about other bus cycle if nWE/nRE is in high state (see nand
datasheets).

So the arbitration is done with nWE/nRE line and without nCE.

Matthieu