From: John Crispin <blogic@openwrt.org>
To: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: linux-mips@linux-mips.org, linux-mtd@lists.infradead.org,
Ralph Hempel <ralph.hempel@lantiq.com>,
David Woodhouse <dwmw2@infradead.org>,
Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH 06/10] MIPS: lantiq: add NOR flash support
Date: Tue, 11 Jan 2011 11:29:52 +0100 [thread overview]
Message-ID: <4D2C3120.80602@openwrt.org> (raw)
In-Reply-To: <4D2BC787.20002@gmail.com>
On 11/01/11 03:59, Daniel Schwierzeck wrote:
> Hi John,
>
> the EBU doesn't allow unaligned read or write access thus Lantiq added
> this alignment hack directly in hardware. The addr^=2 is only needed
> during CFI probe because odd addresses are accessed. A simple solution
> is inside your patch.
>
> The spin_lock_irqsave(&ebu_lock, flags); is actually not needed
> because the EBU does access arbitration and protection already in
> hardware.
>
> Daniel
>
Hi Daniel,
thx, i will try it out later on and then merge it into v2 of the series.
John
next prev parent reply other threads:[~2011-01-11 10:29 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1294257379-417-1-git-send-email-blogic@openwrt.org>
2011-01-05 19:56 ` [PATCH 06/10] MIPS: lantiq: add NOR flash support John Crispin
2011-01-11 2:59 ` Daniel Schwierzeck
2011-01-11 10:29 ` John Crispin [this message]
2011-01-05 19:56 ` [PATCH 07/10] MIPS: lantiq: add NOR flash CFI address swizzle John Crispin
2011-01-06 10:06 ` John Crispin
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