* [PATCH 06/10] MIPS: lantiq: add NOR flash support [not found] <1294257379-417-1-git-send-email-blogic@openwrt.org> @ 2011-01-05 19:56 ` John Crispin 2011-01-11 2:59 ` Daniel Schwierzeck 2011-01-05 19:56 ` [PATCH 07/10] MIPS: lantiq: add NOR flash CFI address swizzle John Crispin 1 sibling, 1 reply; 5+ messages in thread From: John Crispin @ 2011-01-05 19:56 UTC (permalink / raw) To: Ralf Baechle Cc: linux-mips, Ralph Hempel, David Woodhouse, linux-mtd, John Crispin NOR flash is attached to the same EBU (External Bus Unit) as PCI. As described in the PCI patch, the EBU is a little obscure, resulting in the upper and lower 16 bit of the data on a 32 bit read are swapped. (essentially we have a addr^=2) This only happens on the read of data. In order to not have to high an impact on the read performance from the EBU we store all data on the flash with addr^=2. This allows us to do generic reads without having to do any swapping. For the write to now work we need to swizzle the the 0x2 bit of the addr. However this write swizzle needs to only happen when doing a CMD and not a DATA write. As the MTD layer currently makes no difference between a CMD and DATA read when using complex maps, the map driver does not know when the swizzle and when not to swizzle. The next patch in the series adds a hack to the MTD to workaround this problem. I am sending these 2 patches to the mtd list aswell. There are several ways to solve this generically in the mtd layer in a much better way. This will have minor impact on the actual map code provided in this patch. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org --- drivers/mtd/maps/Kconfig | 7 ++ drivers/mtd/maps/Makefile | 1 + drivers/mtd/maps/lantiq.c | 169 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 177 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/maps/lantiq.c diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index a0dd7bb..ca69a7f 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -260,6 +260,13 @@ config MTD_BCM963XX Support for parsing CFE image tag and creating MTD partitions on Broadcom BCM63xx boards. +config MTD_LANTIQ + bool "Lantiq SoC NOR support" + depends on LANTIQ && MTD_PARTITIONS + help + Support for NOR flash chips on Lantiq SoC. The Chips are connected + to the SoCs EBU (External Bus Unit) + config MTD_DILNETPC tristate "CFI Flash device mapped on DIL/Net PC" depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index c7869c7..bb2ce2f 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -59,3 +59,4 @@ obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o obj-$(CONFIG_MTD_VMU) += vmu-flash.o obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o +obj-$(CONFIG_MTD_LANTIQ) += lantiq.o diff --git a/drivers/mtd/maps/lantiq.c b/drivers/mtd/maps/lantiq.c new file mode 100644 index 0000000..e5a361e --- /dev/null +++ b/drivers/mtd/maps/lantiq.c @@ -0,0 +1,169 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/map.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/cfi.h> +#include <linux/magic.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> + +#include <lantiq_soc.h> +#include <lantiq_platform.h> + +static map_word +ltq_read16(struct map_info *map, unsigned long adr) +{ + unsigned long flags; + map_word temp; + spin_lock_irqsave(&ebu_lock, flags); + adr ^= 2; + temp.x[0] = *((__u16 *)(map->virt + adr)); + spin_unlock_irqrestore(&ebu_lock, flags); + return temp; +} + +static void +ltq_write16(struct map_info *map, map_word d, unsigned long adr) +{ + unsigned long flags; + spin_lock_irqsave(&ebu_lock, flags); + adr ^= 2; + *((__u16 *)(map->virt + adr)) = d.x[0]; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +void +ltq_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + unsigned char *p; + unsigned char *to_8; + unsigned long flags; + spin_lock_irqsave(&ebu_lock, flags); + from = (unsigned long)(from + map->virt); + p = (unsigned char *) from; + to_8 = (unsigned char *) to; + while (len--) + *to_8++ = *p++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +void +ltq_copy_to(struct map_info *map, unsigned long to, + const void *from, ssize_t len) +{ + unsigned char *p = (unsigned char *)from; + unsigned char *to_8; + unsigned long flags; + spin_lock_irqsave(&ebu_lock, flags); + to += (unsigned long) map->virt; + to_8 = (unsigned char *)to; + while (len--) + *p++ = *to_8++; + spin_unlock_irqrestore(&ebu_lock, flags); +} + +static const char * const part_probe_types[] = { + "cmdlinepart", NULL }; + +static struct map_info ltq_map = { + .name = "ltq_nor", + .bankwidth = 2, + .read = ltq_read16, + .write = ltq_write16, + .copy_from = ltq_copy_from, + .copy_to = ltq_copy_to, +}; + +static int +ltq_mtd_probe(struct platform_device *pdev) +{ + struct physmap_flash_data *ltq_mtd_data = + (struct physmap_flash_data *) dev_get_platdata(&pdev->dev); + struct mtd_info *ltq_mtd = NULL; + struct mtd_partition *parts = NULL; + struct resource *res = 0; + int nr_parts = 0; + +#ifdef CONFIG_SOC_TYPE_XWAY + ltq_w32(ltq_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); +#endif + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory resource"); + return -ENOENT; + } + res = request_mem_region(res->start, resource_size(res), + dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request mem resource"); + return -EBUSY; + } + + ltq_map.phys = res->start; + ltq_map.size = resource_size(res); + ltq_map.virt = ioremap_nocache(ltq_map.phys, ltq_map.size); + + if (!ltq_map.virt) { + dev_err(&pdev->dev, "failed to ioremap!\n"); + return -EIO; + } + + ltq_mtd = (struct mtd_info *) do_map_probe("cfi_probe", <q_map); + if (!ltq_mtd) { + iounmap(ltq_map.virt); + dev_err(&pdev->dev, "probing failed\n"); + return -ENXIO; + } + + ltq_mtd->owner = THIS_MODULE; + + nr_parts = parse_mtd_partitions(ltq_mtd, part_probe_types, &parts, 0); + if (nr_parts > 0) { + dev_info(&pdev->dev, + "using %d partitions from cmdline", nr_parts); + } else { + nr_parts = ltq_mtd_data->nr_parts; + parts = ltq_mtd_data->parts; + } + + add_mtd_partitions(ltq_mtd, parts, nr_parts); + return 0; +} + +static struct platform_driver ltq_mtd_driver = { + .probe = ltq_mtd_probe, + .driver = { + .name = "ltq_nor", + .owner = THIS_MODULE, + }, +}; + +int __init +init_ltq_mtd(void) +{ + int ret = platform_driver_register(<q_mtd_driver); + if (ret) + printk(KERN_INFO "ltq_nor: error registering platfom driver"); + return ret; +} + +module_init(init_ltq_mtd); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); +MODULE_DESCRIPTION("Lantiq SoC NOR"); -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 06/10] MIPS: lantiq: add NOR flash support 2011-01-05 19:56 ` [PATCH 06/10] MIPS: lantiq: add NOR flash support John Crispin @ 2011-01-11 2:59 ` Daniel Schwierzeck 2011-01-11 10:29 ` John Crispin 0 siblings, 1 reply; 5+ messages in thread From: Daniel Schwierzeck @ 2011-01-11 2:59 UTC (permalink / raw) To: John Crispin Cc: linux-mips, linux-mtd, Ralph Hempel, David Woodhouse, Ralf Baechle Hi John, the EBU doesn't allow unaligned read or write access thus Lantiq added this alignment hack directly in hardware. The addr^=2 is only needed during CFI probe because odd addresses are accessed. A simple solution is inside your patch. The spin_lock_irqsave(&ebu_lock, flags); is actually not needed because the EBU does access arbitration and protection already in hardware. Daniel On 01/05/2011 08:56 PM, John Crispin wrote: > NOR flash is attached to the same EBU (External Bus Unit) as PCI. As described > in the PCI patch, the EBU is a little obscure, resulting in the upper and lower > 16 bit of the data on a 32 bit read are swapped. (essentially we have a addr^=2) > This only happens on the read of data. In order to not have to high an impact > on the read performance from the EBU we store all data on the flash with > addr^=2. This allows us to do generic reads without having to do any swapping. > For the write to now work we need to swizzle the the 0x2 bit of the addr. > However this write swizzle needs to only happen when doing a CMD and not a DATA > write. > > As the MTD layer currently makes no difference between a CMD and DATA read when > using complex maps, the map driver does not know when the swizzle and when not > to swizzle. The next patch in the series adds a hack to the MTD to workaround > this problem. I am sending these 2 patches to the mtd list aswell. There are > several ways to solve this generically in the mtd layer in a much better way. > This will have minor impact on the actual map code provided in this patch. > > Signed-off-by: John Crispin<blogic@openwrt.org> > Signed-off-by: Ralph Hempel<ralph.hempel@lantiq.com> > Cc: David Woodhouse<dwmw2@infradead.org> > Cc: linux-mips@linux-mips.org > Cc: linux-mtd@lists.infradead.org > --- > drivers/mtd/maps/Kconfig | 7 ++ > drivers/mtd/maps/Makefile | 1 + > drivers/mtd/maps/lantiq.c | 169 +++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 177 insertions(+), 0 deletions(-) > create mode 100644 drivers/mtd/maps/lantiq.c > > diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig > index a0dd7bb..ca69a7f 100644 > --- a/drivers/mtd/maps/Kconfig > +++ b/drivers/mtd/maps/Kconfig > @@ -260,6 +260,13 @@ config MTD_BCM963XX > Support for parsing CFE image tag and creating MTD partitions on > Broadcom BCM63xx boards. > > +config MTD_LANTIQ > + bool "Lantiq SoC NOR support" > + depends on LANTIQ&& MTD_PARTITIONS > + help > + Support for NOR flash chips on Lantiq SoC. The Chips are connected > + to the SoCs EBU (External Bus Unit) > + > config MTD_DILNETPC > tristate "CFI Flash device mapped on DIL/Net PC" > depends on X86&& MTD_CONCAT&& MTD_PARTITIONS&& MTD_CFI_INTELEXT&& BROKEN > diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile > index c7869c7..bb2ce2f 100644 > --- a/drivers/mtd/maps/Makefile > +++ b/drivers/mtd/maps/Makefile > @@ -59,3 +59,4 @@ obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o > obj-$(CONFIG_MTD_VMU) += vmu-flash.o > obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o > obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o > +obj-$(CONFIG_MTD_LANTIQ) += lantiq.o > diff --git a/drivers/mtd/maps/lantiq.c b/drivers/mtd/maps/lantiq.c > new file mode 100644 > index 0000000..e5a361e > --- /dev/null > +++ b/drivers/mtd/maps/lantiq.c > @@ -0,0 +1,169 @@ > +/* > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + * > + * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE > + * Copyright (C) 2010 John Crispin<blogic@openwrt.org> > + */ > + > +#include<linux/module.h> > +#include<linux/types.h> > +#include<linux/kernel.h> > +#include<linux/io.h> > +#include<linux/init.h> > +#include<linux/mtd/mtd.h> > +#include<linux/mtd/map.h> > +#include<linux/mtd/partitions.h> > +#include<linux/mtd/cfi.h> > +#include<linux/magic.h> > +#include<linux/platform_device.h> > +#include<linux/mtd/physmap.h> > + > +#include<lantiq_soc.h> > +#include<lantiq_platform.h> > + static int ltq_probing = 0; > +static map_word > +ltq_read16(struct map_info *map, unsigned long adr) > +{ > + unsigned long flags; > + map_word temp; > + spin_lock_irqsave(&ebu_lock, flags); if (ltq_probing) adr ^= 2; > + temp.x[0] = *((__u16 *)(map->virt + adr)); > + spin_unlock_irqrestore(&ebu_lock, flags); > + return temp; > +} > + > +static void > +ltq_write16(struct map_info *map, map_word d, unsigned long adr) > +{ > + unsigned long flags; > + spin_lock_irqsave(&ebu_lock, flags); if (ltq_probing) adr ^= 2; > + *((__u16 *)(map->virt + adr)) = d.x[0]; > + spin_unlock_irqrestore(&ebu_lock, flags); > +} > + > +void > +ltq_copy_from(struct map_info *map, void *to, > + unsigned long from, ssize_t len) > +{ > + unsigned char *p; > + unsigned char *to_8; > + unsigned long flags; > + spin_lock_irqsave(&ebu_lock, flags); > + from = (unsigned long)(from + map->virt); > + p = (unsigned char *) from; > + to_8 = (unsigned char *) to; > + while (len--) > + *to_8++ = *p++; > + spin_unlock_irqrestore(&ebu_lock, flags); > +} > + > +void > +ltq_copy_to(struct map_info *map, unsigned long to, > + const void *from, ssize_t len) > +{ > + unsigned char *p = (unsigned char *)from; > + unsigned char *to_8; > + unsigned long flags; > + spin_lock_irqsave(&ebu_lock, flags); > + to += (unsigned long) map->virt; > + to_8 = (unsigned char *)to; > + while (len--) > + *p++ = *to_8++; > + spin_unlock_irqrestore(&ebu_lock, flags); > +} > + > +static const char * const part_probe_types[] = { > + "cmdlinepart", NULL }; > + > +static struct map_info ltq_map = { > + .name = "ltq_nor", > + .bankwidth = 2, > + .read = ltq_read16, > + .write = ltq_write16, > + .copy_from = ltq_copy_from, > + .copy_to = ltq_copy_to, > +}; > + > +static int > +ltq_mtd_probe(struct platform_device *pdev) > +{ > + struct physmap_flash_data *ltq_mtd_data = > + (struct physmap_flash_data *) dev_get_platdata(&pdev->dev); > + struct mtd_info *ltq_mtd = NULL; > + struct mtd_partition *parts = NULL; > + struct resource *res = 0; > + int nr_parts = 0; > + > +#ifdef CONFIG_SOC_TYPE_XWAY > + ltq_w32(ltq_r32(LTQ_EBU_BUSCON0)& ~EBU_WRDIS, LTQ_EBU_BUSCON0); > +#endif > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) { > + dev_err(&pdev->dev, "failed to get memory resource"); > + return -ENOENT; > + } > + res = request_mem_region(res->start, resource_size(res), > + dev_name(&pdev->dev)); > + if (!res) { > + dev_err(&pdev->dev, "failed to request mem resource"); > + return -EBUSY; > + } > + > + ltq_map.phys = res->start; > + ltq_map.size = resource_size(res); > + ltq_map.virt = ioremap_nocache(ltq_map.phys, ltq_map.size); > + > + if (!ltq_map.virt) { > + dev_err(&pdev->dev, "failed to ioremap!\n"); > + return -EIO; > + } > + ltq_probing = 1; > + ltq_mtd = (struct mtd_info *) do_map_probe("cfi_probe",<q_map); ltq_probing = 0; > + if (!ltq_mtd) { > + iounmap(ltq_map.virt); > + dev_err(&pdev->dev, "probing failed\n"); > + return -ENXIO; > + } > + > + ltq_mtd->owner = THIS_MODULE; > + > + nr_parts = parse_mtd_partitions(ltq_mtd, part_probe_types,&parts, 0); > + if (nr_parts> 0) { > + dev_info(&pdev->dev, > + "using %d partitions from cmdline", nr_parts); > + } else { > + nr_parts = ltq_mtd_data->nr_parts; > + parts = ltq_mtd_data->parts; > + } > + > + add_mtd_partitions(ltq_mtd, parts, nr_parts); > + return 0; > +} > + > +static struct platform_driver ltq_mtd_driver = { > + .probe = ltq_mtd_probe, > + .driver = { > + .name = "ltq_nor", > + .owner = THIS_MODULE, > + }, > +}; > + > +int __init > +init_ltq_mtd(void) > +{ > + int ret = platform_driver_register(<q_mtd_driver); > + if (ret) > + printk(KERN_INFO "ltq_nor: error registering platfom driver"); > + return ret; > +} > + > +module_init(init_ltq_mtd); > + > +MODULE_LICENSE("GPL"); > +MODULE_AUTHOR("John Crispin<blogic@openwrt.org>"); > +MODULE_DESCRIPTION("Lantiq SoC NOR"); ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 06/10] MIPS: lantiq: add NOR flash support 2011-01-11 2:59 ` Daniel Schwierzeck @ 2011-01-11 10:29 ` John Crispin 0 siblings, 0 replies; 5+ messages in thread From: John Crispin @ 2011-01-11 10:29 UTC (permalink / raw) To: Daniel Schwierzeck Cc: linux-mips, linux-mtd, Ralph Hempel, David Woodhouse, Ralf Baechle On 11/01/11 03:59, Daniel Schwierzeck wrote: > Hi John, > > the EBU doesn't allow unaligned read or write access thus Lantiq added > this alignment hack directly in hardware. The addr^=2 is only needed > during CFI probe because odd addresses are accessed. A simple solution > is inside your patch. > > The spin_lock_irqsave(&ebu_lock, flags); is actually not needed > because the EBU does access arbitration and protection already in > hardware. > > Daniel > Hi Daniel, thx, i will try it out later on and then merge it into v2 of the series. John ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 07/10] MIPS: lantiq: add NOR flash CFI address swizzle [not found] <1294257379-417-1-git-send-email-blogic@openwrt.org> 2011-01-05 19:56 ` [PATCH 06/10] MIPS: lantiq: add NOR flash support John Crispin @ 2011-01-05 19:56 ` John Crispin 2011-01-06 10:06 ` John Crispin 1 sibling, 1 reply; 5+ messages in thread From: John Crispin @ 2011-01-05 19:56 UTC (permalink / raw) To: Ralf Baechle Cc: linux-mips, Ralph Hempel, David Woodhouse, linux-mtd, John Crispin This patch adds the hack mentioned in the previous patch. It is only a hack to make the map driver work until a better solution is discussed. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org --- drivers/mtd/chips/Kconfig | 9 +++++++++ drivers/mtd/chips/cfi_cmdset_0002.c | 8 ++++++++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/chips/Kconfig b/drivers/mtd/chips/Kconfig index 35c6a23..9ecb5eb 100644 --- a/drivers/mtd/chips/Kconfig +++ b/drivers/mtd/chips/Kconfig @@ -39,6 +39,15 @@ config MTD_CFI_ADV_OPTIONS If unsure, say 'N'. +config MTD_CFI_CMD_SWIZZLE + bool "Swizzle last bit of command address" + default y + depends on LANTIQ + help + lantiq SoCs share the external bus unit with the pci interface + for MTD to work at the the same time with PCI, we need to add + this quirk + choice prompt "Flash cmd/query data swapping" depends on MTD_CFI_ADV_OPTIONS diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c index 3b8e32d..e047af1 100644 --- a/drivers/mtd/chips/cfi_cmdset_0002.c +++ b/drivers/mtd/chips/cfi_cmdset_0002.c @@ -39,7 +39,12 @@ #include <linux/mtd/xip.h> #define AMD_BOOTLOC_BUG + +#ifdef CONFIG_MTD_CFI_CMD_SWIZZLE +#define FORCE_WORD_WRITE 1 +#else #define FORCE_WORD_WRITE 0 +#endif #define MAX_WORD_RETRIES 3 @@ -1140,6 +1145,9 @@ static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, int retry_cnt = 0; adr += chip->start; +#ifdef CONFIG_MTD_CFI_CMD_SWIZZLE + adr ^= 2; +#endif mutex_lock(&chip->mutex); ret = get_chip(map, chip, adr, FL_WRITING); -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 07/10] MIPS: lantiq: add NOR flash CFI address swizzle 2011-01-05 19:56 ` [PATCH 07/10] MIPS: lantiq: add NOR flash CFI address swizzle John Crispin @ 2011-01-06 10:06 ` John Crispin 0 siblings, 0 replies; 5+ messages in thread From: John Crispin @ 2011-01-06 10:06 UTC (permalink / raw) To: David Woodhouse; +Cc: linux-mips, Ralph Hempel, linux-mtd, Ralf Baechle On 05/01/11 20:56, John Crispin wrote: > > adr += chip->start; > +#ifdef CONFIG_MTD_CFI_CMD_SWIZZLE > + adr ^= 2; > +#endif > > mutex_lock(&chip->mutex); > ret = get_chip(map, chip, adr, FL_WRITING); > Hi, What this patch essentially does is to make sure to pass a addr with the ^=2 hack already applied, so that the complex map ends up with an un swizzled addr as it applies the hack internally again. I think it would be cleanest to extend the read/write callbacks of struct map_info; with a flag indicating whether we are doing a CMD or DATA action. as the 2 following macros are used anyway, it should not be too hard to implement this. #define map_read(map, ofs) (map)->read(map, ofs) #define map_write(map, datum, ofs) (map)->write(map, datum, ofs) I am not sure however if this is the correct fix. Thanks, John ^ permalink raw reply [flat|nested] 5+ messages in thread
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2011-01-05 19:56 ` [PATCH 06/10] MIPS: lantiq: add NOR flash support John Crispin
2011-01-11 2:59 ` Daniel Schwierzeck
2011-01-11 10:29 ` John Crispin
2011-01-05 19:56 ` [PATCH 07/10] MIPS: lantiq: add NOR flash CFI address swizzle John Crispin
2011-01-06 10:06 ` John Crispin
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