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From: John Crispin <blogic@openwrt.org>
To: Sergei Shtylyov <sshtylyov@mvista.com>
Cc: linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
	Ralph Hempel <ralph.hempel@lantiq.com>,
	linux-mtd@lists.infradead.org,
	Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH V3 06/10] MIPS: lantiq: add NOR flash support
Date: Fri, 04 Mar 2011 21:13:00 +0100	[thread overview]
Message-ID: <4D7147CC.1020009@openwrt.org> (raw)
In-Reply-To: <4D70DDEA.2050308@mvista.com>

Hi,

>> +    if (ltq_mtd_probing)
>> +        adr ^= 2;
>> +    spin_lock_irqsave(&ebu_lock, flags);
>> +    temp.x[0] = *((__u16 *)(map->virt + adr));
>> +    spin_unlock_irqrestore(&ebu_lock, flags);
>
>    Hm, what does this lock gain, if the read is atomic anyway?

the SoC has a hardware arbitor for the EBU. I have so far not been able
to activate it properly and the lock is needed to protect from PCI and
NOR i/o clashing with eachother. i know that the arbitor works when
using lantiqs 2.6.28. i will provide a follow up patch once i figured
how to bring up the arbitor properly. until that time we need to use the
lock.

thanks,
John

      parent reply	other threads:[~2011-03-04 20:11 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1299146626-17428-1-git-send-email-blogic@openwrt.org>
2011-03-03 10:03 ` [PATCH V3 06/10] MIPS: lantiq: add NOR flash support John Crispin
2011-03-04 12:41   ` Sergei Shtylyov
2011-03-04 15:10     ` Sergei Shtylyov
2011-03-04 20:13     ` John Crispin [this message]

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