Re: [PATCH 1/7] ARM: add GPMI support for imx23/imx28

Re: [PATCH 1/7] ARM: add GPMI support for imx23/imx28

[Huang Shijie]

Hi:

> Huang Shijie writes:
>> Hi Lothar:
>>> Hi,
>>>
>>> All in all I do not like this driver in any way. I already vomitted
>>> over it, when I saw it in the Freescale BSP.
>> :)  I have already removed a lot of code.
>>
>>> There is no need for the multiple layers of abstraction that are
>>> papered over the MTD layer.
>> I think this is good. Make the code clear.
>>
> I'll comment when the remaining patch has got through.
>
thanks a lot .


>>> There is no need for spilling the driver over a dozen files.
>> I can merge some files into one. thanks.
>>
> IMO all the source code could be kept in one file (except for the
> include files of course) and the gpmi-nfc subdirectory removed.
I really can merge some files, but IMHO, it's not a good solution to 
keep all in one file.

The reasons are :
[1] The GPMI support the NAND boot mode,but the imx23 and imx28 is a 
little different in
the NAND boot procedure due the different firmwares in the chips. If I 
merge the rom-imx23.c
rom-imx28.c to one file, the code will very mess. ugly enough!

[2]The GPMI driver is just a mini version against the version in the 
FREESCALE BSP.
The original GPMI driver also support the IMX508 which is different from 
the imx23 and imx28.
The imx508 supports the ONFI NAND and TOGGLE NAND which are DDR mode 
NAND.So the implement of
ECC read_page/write_page is much different from the IMX23/IMX28. Because 
I want to support the
IMX508 in future, this is why the hal-imx23.c and hal-imx28.c share most 
the same code,but i still
remain them in separate, the reason is simple : I will add a 
hal-imx508.c in future.

[3]The GPMI driver is a little complicated. The GPMI controller needs 
other two hardware module to
work :the BCH module, and the DMA mode.
      Yes, i can merge the DMA code into other files, but the BCH module 
should occupy a separate file to
make the logic clear.

[4] If i packet all the code in one, the gentlemen of MTD mailist, such 
as David Woodhouse, Artem Bityutskiy ,
will kill me, :).  what's more the big boy even can not be emailed to 
arm-kernel maillist.


> I've been working on this too, but had to abandone it for other tasks
> several times. :(
>
I really apreciate for your review and comments. I just want to make the 
drive tidy and grace.

Please point out the ugly part that you regards in free.

I am very glad you had ever tried to work on this. :)


Best Regards
Huang Shijie

Re: [PATCH 1/7] ARM: add GPMI support for imx23/imx28

[Lothar Waßmann]

Hi,

Huang Shijie writes:
> Hi:
> 
> > Huang Shijie writes:
> >> Hi Lothar:
> >>> Hi,
> >>>
> >>> All in all I do not like this driver in any way. I already vomitted
> >>> over it, when I saw it in the Freescale BSP.
> >> :)  I have already removed a lot of code.
> >>
> >>> There is no need for the multiple layers of abstraction that are
> >>> papered over the MTD layer.
> >> I think this is good. Make the code clear.
> >>
> > I'll comment when the remaining patch has got through.
> >
> thanks a lot .
> 
> 
> >>> There is no need for spilling the driver over a dozen files.
> >> I can merge some files into one. thanks.
> >>
> > IMO all the source code could be kept in one file (except for the
> > include files of course) and the gpmi-nfc subdirectory removed.
> I really can merge some files, but IMHO, it's not a good solution to 
> keep all in one file.
> 
> The reasons are :
> [1] The GPMI support the NAND boot mode,but the imx23 and imx28 is a 
> little different in
> the NAND boot procedure due the different firmwares in the chips. If I 
> merge the rom-imx23.c
> rom-imx28.c to one file, the code will very mess. ugly enough!
> 
You can use platform_ids to differentiate between the versions and
have separate functions for imx23 and imx28 where appropriate and
select between those depending on the platform_id.


Lothar Waßmann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________

Re: [PATCH 1/7] ARM: add GPMI support for imx23/imx28

[Huang Shijie]

hi:

>>> IMO all the source code could be kept in one file (except for the
>>> include files of course) and the gpmi-nfc subdirectory removed.
>> I really can merge some files, but IMHO, it's not a good solution to
>> keep all in one file.
>>
>> The reasons are :
>> [1] The GPMI support the NAND boot mode,but the imx23 and imx28 is a
>> little different in
>> the NAND boot procedure due the different firmwares in the chips. If I
>> merge the rom-imx23.c
>> rom-imx28.c to one file, the code will very mess. ugly enough!
>>
> You can use platform_ids to differentiate between the versions and
> have separate functions for imx23 and imx28 where appropriate and
> select between those depending on the platform_id.
>
>
thanks a lot.


Best Regards.
Huang Shijie

Re: [PATCH 5/7] add GPMI support for imx28

[Huang Shijie]

Hi Lothar:

    Thanks a lot for your carefully review.


> Hi,
>
> some general comments:
> - Why are you not using the existing nand_ids but inventing your own
>    database?
>
The nand_ids{} contains poor information for me.
Such as :
[1]The nand_ids does not have the enough information for the page 
size,oob size for some new NANDs.
    And you can not get the information from parsing the NAND ids, such 
as some Micron NANDs.

[2]I need the timing information of the NAND. The nand_ids DOES not have 
it. I have to
    read the datasheet of the NAND, and add it to my database.

[3]I need the information about the error Management for BCH.
    The BCH module needs to know the ECC information of the NAND, the 
nand_ids{} does not have it.
Different NANDs may have different ECC requires such as "Minimum 
required ECC".


> - What is the purpose of the 'rom_helpers'? To me it looks like they
>    are doing something that should be done in the mtd partition
>    handlers, not in the flash chip driver.
>
We have saled a lot products based the imx23 or imx28.
All the products support the nand boot mode by flashing the kernel to 
the kernel partitions of the nands.
In order to compliant to the old product, the layout of the nand is 
constraint to the current situation:
[1] first a boot partition for the kernel.
[2] the rest is for other uses, such as rootfs.

So I have to use the rom_helpers to split the kernel partition before 
the real MTD partition initializations.



> Huang Shijie writes:
>> These files contain the code to implement the GPMI in the imx28.
>>
>> Signed-off-by: Huang Shijie<b32955@freescale.com>
>> ---
>>   drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h  |  557 +++++++++++++++++++++++++++
>>   drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h |  421 ++++++++++++++++++++
>>   drivers/mtd/nand/gpmi-nfc/hal-imx28.c       |  503 ++++++++++++++++++++++++
>>   drivers/mtd/nand/gpmi-nfc/rom-imx28.c       |   66 ++++
>>   4 files changed, 1547 insertions(+), 0 deletions(-)
>>   create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
>>   create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
>>   create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx28.c
>>   create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx28.c
>>
>> diff --git a/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
>> new file mode 100644
>> index 0000000..692db08
>> --- /dev/null
>> +++ b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
>> @@ -0,0 +1,557 @@
>> +/*
>> + * Freescale GPMI NFC NAND Flash Driver
>> + *
>> + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
>> + *
>> + * Xml Revision: 2.5
>> + * Template revision: 26195
>> + */
>> +
>> +#ifndef __GPMI_NFC_BCH_REGS_H
>> +#define __GPMI_NFC_BCH_REGS_H
>> +
>> +/*============================================================================*/
>> +
>> +#define HW_BCH_CTRL	(0x00000000)
>> +#define HW_BCH_CTRL_SET	(0x00000004)
>> +#define HW_BCH_CTRL_CLR	(0x00000008)
>> +#define HW_BCH_CTRL_TOG	(0x0000000c)
>>
> No need for parens around bare numbers.
>
Ok. Frankly speaking, the file is auto created by some tools from the 
hardware info.
>> +#define BM_BCH_CTRL_SFTRST	0x80000000
>> +#define BV_BCH_CTRL_SFTRST__RUN   0x0
>> +#define BV_BCH_CTRL_SFTRST__RESET 0x1
>> +#define BM_BCH_CTRL_CLKGATE	0x40000000
>> +#define BV_BCH_CTRL_CLKGATE__RUN     0x0
>> +#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
>> +#define BP_BCH_CTRL_RSVD5	23
>> +#define BM_BCH_CTRL_RSVD5	0x3F800000
>> +#define BF_BCH_CTRL_RSVD5(v)  \
>> +		(((v)<<  23)&  BM_BCH_CTRL_RSVD5)
>> +#define BM_BCH_CTRL_DEBUGSYNDROME	0x00400000
>> +#define BP_BCH_CTRL_RSVD4	20
>> +#define BM_BCH_CTRL_RSVD4	0x00300000
>> +#define BF_BCH_CTRL_RSVD4(v)  \
>> +		(((v)<<  20)&  BM_BCH_CTRL_RSVD4)
>> +#define BP_BCH_CTRL_M2M_LAYOUT	18
>> +#define BM_BCH_CTRL_M2M_LAYOUT	0x000C0000
>> +#define BF_BCH_CTRL_M2M_LAYOUT(v)  \
>> +		(((v)<<  18)&  BM_BCH_CTRL_M2M_LAYOUT)
>> +#define BM_BCH_CTRL_M2M_ENCODE	0x00020000
>> +#define BM_BCH_CTRL_M2M_ENABLE	0x00010000
>> +#define BP_BCH_CTRL_RSVD3	11
>> +#define BM_BCH_CTRL_RSVD3	0x0000F800
>> +#define BF_BCH_CTRL_RSVD3(v)  \
>> +		(((v)<<  11)&  BM_BCH_CTRL_RSVD3)
>> +#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN	0x00000400
>> +#define BM_BCH_CTRL_RSVD2	0x00000200
>> +#define BM_BCH_CTRL_COMPLETE_IRQ_EN	0x00000100
>> +#define BP_BCH_CTRL_RSVD1	4
>> +#define BM_BCH_CTRL_RSVD1	0x000000F0
>> +#define BF_BCH_CTRL_RSVD1(v)  \
>> +		(((v)<<  4)&  BM_BCH_CTRL_RSVD1)
>> +#define BM_BCH_CTRL_BM_ERROR_IRQ	0x00000008
>> +#define BM_BCH_CTRL_DEBUG_STALL_IRQ	0x00000004
>> +#define BM_BCH_CTRL_RSVD0	0x00000002
>> +#define BM_BCH_CTRL_COMPLETE_IRQ	0x00000001
>> +
> [...]
> Messed up indentation. Also, use TAB instead of spaces for indentation.
>
ditto
>> diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
>> new file mode 100644
>> index 0000000..dcb3b7d
>> --- /dev/null
>> +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
>> @@ -0,0 +1,421 @@
>> +/*
>> + * Freescale GPMI NFC NAND Flash Driver
>> + *
>> + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
>> + *
>> + * Xml Revision: 2.2
>> + * Template revision: 26195
>> + */
>> +
>> +#ifndef __GPMI_NFC_GPMI_REGS_H
>> +#define __GPMI_NFC_GPMI_REGS_H
>> +
>> +/*============================================================================*/
>> +
>> +#define HW_GPMI_CTRL0	(0x00000000)
>> +#define HW_GPMI_CTRL0_SET	(0x00000004)
>> +#define HW_GPMI_CTRL0_CLR	(0x00000008)
>> +#define HW_GPMI_CTRL0_TOG	(0x0000000c)
>> +
>> +#define BM_GPMI_CTRL0_SFTRST	0x80000000
>> +#define BV_GPMI_CTRL0_SFTRST__RUN   0x0
>> +#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
>> +#define BM_GPMI_CTRL0_CLKGATE	0x40000000
>> +#define BV_GPMI_CTRL0_CLKGATE__RUN     0x0
>> +#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
>> +#define BM_GPMI_CTRL0_RUN	0x20000000
>> +#define BV_GPMI_CTRL0_RUN__IDLE 0x0
>> +#define BV_GPMI_CTRL0_RUN__BUSY 0x1
>> +#define BM_GPMI_CTRL0_DEV_IRQ_EN	0x10000000
>> +#define BM_GPMI_CTRL0_LOCK_CS	0x08000000
>> +#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
>> +#define BV_GPMI_CTRL0_LOCK_CS__ENABLED  0x1
>> +#define BM_GPMI_CTRL0_UDMA	0x04000000
>> +#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
>> +#define BV_GPMI_CTRL0_UDMA__ENABLED  0x1
>> +#define BP_GPMI_CTRL0_COMMAND_MODE	24
>> +#define BM_GPMI_CTRL0_COMMAND_MODE	0x03000000
>> +#define BF_GPMI_CTRL0_COMMAND_MODE(v)  \
>> +		(((v)<<  24)&  BM_GPMI_CTRL0_COMMAND_MODE)
>> +#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE            0x0
>> +#define BV_GPMI_CTRL0_COMMAND_MODE__READ             0x1
>> +#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
>> +#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY   0x3
>> +#define BM_GPMI_CTRL0_WORD_LENGTH	0x00800000
>> +#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
>> +#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT  0x1
>> +#define BP_GPMI_CTRL0_CS	20
>> +#define BM_GPMI_CTRL0_CS	0x00700000
>> +#define BF_GPMI_CTRL0_CS(v)  \
>> +		(((v)<<  20)&  BM_GPMI_CTRL0_CS)
>> +#define BP_GPMI_CTRL0_ADDRESS	17
>> +#define BM_GPMI_CTRL0_ADDRESS	0x000E0000
>> +#define BF_GPMI_CTRL0_ADDRESS(v)  \
>> +		(((v)<<  17)&  BM_GPMI_CTRL0_ADDRESS)
>> +#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
>> +#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE  0x1
>> +#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE  0x2
>> +#define BM_GPMI_CTRL0_ADDRESS_INCREMENT	0x00010000
>> +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
>> +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED  0x1
>> +#define BP_GPMI_CTRL0_XFER_COUNT	0
>> +#define BM_GPMI_CTRL0_XFER_COUNT	0x0000FFFF
>> +#define BF_GPMI_CTRL0_XFER_COUNT(v)  \
>> +		(((v)<<  0)&  BM_GPMI_CTRL0_XFER_COUNT)
>>
> same as above.
>
>> diff --git a/drivers/mtd/nand/gpmi-nfc/hal-imx28.c b/drivers/mtd/nand/gpmi-nfc/hal-imx28.c
>> new file mode 100644
>> index 0000000..ff87d7f
>> --- /dev/null
>> +++ b/drivers/mtd/nand/gpmi-nfc/hal-imx28.c
>> @@ -0,0 +1,503 @@
>> +/*
>> + * Freescale GPMI NFC NAND Flash Driver
>> + *
>> + * Copyright (C) 2011 Freescale Semiconductor, Inc.
>> + * Copyright (C) 2008 Embedded Alley Solutions, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, write to the Free Software Foundation, Inc.,
>> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
>> + */
>> +#include "gpmi-nfc.h"
>> +#include "gpmi-regs-imx28.h"
>> +#include "bch-regs-imx28.h"
>> +
> [...]
>> +static int send_command(struct gpmi_nfc_data *this)
>> +{
>> +	struct dma_chan *channel = get_dma_chan(this);
>> +	struct mil *mil	=&this->mil;
>> +	struct dma_async_tx_descriptor *desc;
>> +	struct scatterlist *sgl;
>> +	u32 pio[3];
>> +
>> +	/* [1] send out the PIO words */
>> +	pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
>> +		| BM_GPMI_CTRL0_WORD_LENGTH
>> +		| BF_GPMI_CTRL0_CS(mil->current_chip)
>> +		| BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
>> +		| BM_GPMI_CTRL0_ADDRESS_INCREMENT
>> +		| BF_GPMI_CTRL0_XFER_COUNT(mil->command_length);
>> +	pio[1] = pio[2] = 0;
>> +	desc = channel->device->device_prep_slave_sg(channel,
>> +					(struct scatterlist *)pio,
>> +					ARRAY_SIZE(pio), DMA_NONE, 0);
>> +	if (!desc) {
>> +		log("step 1 error");
>> +		return -1;
>> +	}
>> +
>> +	/* [2] send out the COMMAND + ADDRESS string stored in @buffer */
>> +	sgl =&mil->cmd_sgl;
>> +
>> +	dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
>> +	sgl->length = mil->command_length;
>>
> this has to be done _before_ dma_map_sg(). With CONFIG_DMA_API_DEBUG
> enabled you would get:
> |gpmi-nfc gpmi-nfc: DMA-API: device driver frees DMA memory with different size [device address=0x0000000046e10000] [map size=4096 bytes] [unmap size=1 bytes]
>
thanks.

Huang Shijie

Re: [PATCH 5/7] add GPMI support for imx28

[Lothar Waßmann]

Hi,

Huang Shijie writes:
> Hi Lothar:
> 
>     Thanks a lot for your carefully review.
> 
> 
> > Hi,
> >
> > some general comments:
> > - Why are you not using the existing nand_ids but inventing your own
> >    database?
> >
> The nand_ids{} contains poor information for me.
> Such as :
> [1]The nand_ids does not have the enough information for the page 
> size,oob size for some new NANDs.
>     And you can not get the information from parsing the NAND ids, such 
> as some Micron NANDs.
> 
You could use it for the standard chips where you do not need
additional information. That way most NAND chips could be supported
out of the box without having to modify the driver.

> [2]I need the timing information of the NAND. The nand_ids DOES not have 
> it. I have to
>     read the datasheet of the NAND, and add it to my database.
> 
Do we really need exact timing data for each individual chip?
Or couldn't we live with some sane timing that works for most chips
and provide some means to specify a different timing via
platform_data?

> > - What is the purpose of the 'rom_helpers'? To me it looks like they
> >    are doing something that should be done in the mtd partition
> >    handlers, not in the flash chip driver.
> >
> We have saled a lot products based the imx23 or imx28.
> All the products support the nand boot mode by flashing the kernel to 
> the kernel partitions of the nands.
> In order to compliant to the old product, the layout of the nand is 
> constraint to the current situation:
> [1] first a boot partition for the kernel.
> [2] the rest is for other uses, such as rootfs.
> 
> So I have to use the rom_helpers to split the kernel partition before 
> the real MTD partition initializations.
> 
Why can't you just create appropriate partitions using the standard
partition handlers?


Lothar Waßmann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________

Re: [PATCH 5/7] add GPMI support for imx28

[Florian Fainelli]

Hello,

On Wednesday 23 March 2011 15:56:24 Lothar Waßmann wrote:
> Hi,
> 
> Huang Shijie writes:
> > Hi Lothar:
> >     Thanks a lot for your carefully review.
> > > 
> > > Hi,
> > > 
> > > some general comments:
> > > - Why are you not using the existing nand_ids but inventing your own
> > > 
> > >    database?
> > 
> > The nand_ids{} contains poor information for me.
> > Such as :
> > [1]The nand_ids does not have the enough information for the page
> > size,oob size for some new NANDs.
> > 
> >     And you can not get the information from parsing the NAND ids, such
> > 
> > as some Micron NANDs.
> 
> You could use it for the standard chips where you do not need
> additional information. That way most NAND chips could be supported
> out of the box without having to modify the driver.
> 
> > [2]I need the timing information of the NAND. The nand_ids DOES not have
> > it. I have to
> > 
> >     read the datasheet of the NAND, and add it to my database.
> 
> Do we really need exact timing data for each individual chip?
> Or couldn't we live with some sane timing that works for most chips
> and provide some means to specify a different timing via
> platform_data?

I suppose this is the way it should be done, but then you might some need some 
sort of NAND detection available before registering the driver. Eventually, 
the bootloader might have configured the appropriate timings already.

Have you considered using ONFI chips? They have standard timings at least.

> 
> > > - What is the purpose of the 'rom_helpers'? To me it looks like they
> > > 
> > >    are doing something that should be done in the mtd partition
> > >    handlers, not in the flash chip driver.
> > 
> > We have saled a lot products based the imx23 or imx28.
> > All the products support the nand boot mode by flashing the kernel to
> > the kernel partitions of the nands.
> > In order to compliant to the old product, the layout of the nand is
> > constraint to the current situation:
> > [1] first a boot partition for the kernel.
> > [2] the rest is for other uses, such as rootfs.
> > 
> > So I have to use the rom_helpers to split the kernel partition before
> > the real MTD partition initializations.
> 
> Why can't you just create appropriate partitions using the standard
> partition handlers?
> 
> 
> Lothar Waßmann

Re: [PATCH 5/7] add GPMI support for imx28

[Huang Shijie]

Hi:
>>>> Hi,
>>>>
>>>> some general comments:
>>>> - Why are you not using the existing nand_ids but inventing your own
>>>>
>>>>     database?
>>> The nand_ids{} contains poor information for me.
>>> Such as :
>>> [1]The nand_ids does not have the enough information for the page
>>> size,oob size for some new NANDs.
>>>
>>>      And you can not get the information from parsing the NAND ids, such
>>>
>>> as some Micron NANDs.
>> You could use it for the standard chips where you do not need
>> additional information. That way most NAND chips could be supported
>> out of the box without having to modify the driver.
>>
>>> [2]I need the timing information of the NAND. The nand_ids DOES not have
>>> it. I have to
>>>
>>>      read the datasheet of the NAND, and add it to my database.
>> Do we really need exact timing data for each individual chip?
>> Or couldn't we live with some sane timing that works for most chips
>> and provide some means to specify a different timing via
>> platform_data?
> I suppose this is the way it should be done, but then you might some need some
> sort of NAND detection available before registering the driver. Eventually,
> the bootloader might have configured the appropriate timings already.
The bootloader does not set it.
> Have you considered using ONFI chips? They have standard timings at least.
>
The imx23/imx28 do not support ONFI chips in the DDR mode due to the 
hardware limits.
The the imx508 does support the ONFI and TOGGLE nand in the DDR mode.


Best Regards
Huang Shijie

Re: [PATCH 5/7] add GPMI support for imx28

[Huang Shijie]

Hi Lothar:
>
>>> some general comments:
>>> - Why are you not using the existing nand_ids but inventing your own
>>>     database?
>>>
>> The nand_ids{} contains poor information for me.
>> Such as :
>> [1]The nand_ids does not have the enough information for the page
>> size,oob size for some new NANDs.
>>      And you can not get the information from parsing the NAND ids, such
>> as some Micron NANDs.
>>
> You could use it for the standard chips where you do not need
> additional information. That way most NAND chips could be supported
> out of the box without having to modify the driver.
>
What the meaning of "standard chips"?

There are many nands in the world. Every vendor has its own rules, some 
even does has :)

Unluckily, the imx23/imx28 supports many nands that the nand_ids{} does 
not support.
I have many nands by my hand. I will add it gradually.

I want to get the page size/oob size from my own database which can not 
get from the nand_ids.


>> [2]I need the timing information of the NAND. The nand_ids DOES not have
>> it. I have to
>>      read the datasheet of the NAND, and add it to my database.
>>
> Do we really need exact timing data for each individual chip?
> Or couldn't we live with some sane timing that works for most chips
> and provide some means to specify a different timing via
> platform_data?
>
Most of the time, the timing is really based on a safe timing setting.
But in the original GPMI driver in the FREESCALE BSP, there exits some
nands need to be set with their own timing setting.

So I do not use the safe timing for _ALL_ the nand, and i'd better get 
it from the
database.
>>> - What is the purpose of the 'rom_helpers'? To me it looks like they
>>>     are doing something that should be done in the mtd partition
>>>     handlers, not in the flash chip driver.
>>>
>> We have saled a lot products based the imx23 or imx28.
>> All the products support the nand boot mode by flashing the kernel to
>> the kernel partitions of the nands.
>> In order to compliant to the old product, the layout of the nand is
>> constraint to the current situation:
>> [1] first a boot partition for the kernel.
>> [2] the rest is for other uses, such as rootfs.
>>
>> So I have to use the rom_helpers to split the kernel partition before
>> the real MTD partition initializations.
>>
> Why can't you just create appropriate partitions using the standard
> partition handlers?
>
thanks , I will try to change the code according to your advice.

Huang Shijie

Re: [PATCH 5/7] add GPMI support for imx28

[Lothar Waßmann]

Hi,

Huang Shijie writes:
> Hi Lothar:
> >
> >>> some general comments:
> >>> - Why are you not using the existing nand_ids but inventing your own
> >>>     database?
> >>>
> >> The nand_ids{} contains poor information for me.
> >> Such as :
> >> [1]The nand_ids does not have the enough information for the page
> >> size,oob size for some new NANDs.
> >>      And you can not get the information from parsing the NAND ids, such
> >> as some Micron NANDs.
> >>
> > You could use it for the standard chips where you do not need
> > additional information. That way most NAND chips could be supported
> > out of the box without having to modify the driver.
> >
> What the meaning of "standard chips"?
> 
Those chips that are supported by other drivers for long time.

> There are many nands in the world. Every vendor has its own rules, some 
> even does has :)
> 
> Unluckily, the imx23/imx28 supports many nands that the nand_ids{} does 
> not support.
>
That's no reason to scrap support for all chips that every other
driver supports.

> I have many nands by my hand. I will add it gradually.
> 
So why not add them to the generic database?

> I want to get the page size/oob size from my own database which can not 
> get from the nand_ids.
> 
If there are parameters needed that cannot be obtained from the
generic database, it might be worth upgrading that database instead of
creating your own local database.

> >> [2]I need the timing information of the NAND. The nand_ids DOES not have
> >> it. I have to
> >>      read the datasheet of the NAND, and add it to my database.
> >>
> > Do we really need exact timing data for each individual chip?
> > Or couldn't we live with some sane timing that works for most chips
> > and provide some means to specify a different timing via
> > platform_data?
> >
> Most of the time, the timing is really based on a safe timing setting.
> But in the original GPMI driver in the FREESCALE BSP, there exits some
> nands need to be set with their own timing setting.
> 
> So I do not use the safe timing for _ALL_ the nand, and i'd better get 
> it from the
> database.
>
It should be sufficient to provide timing info from platform_data in
special cases instead of bloating the nand id database with that
stuff. Platforms might need to adjust the timing because of
peculiarities in the HW. Thus the timing info should be provided from
there, not from the chip database.


Lothar Waßmann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________

Re: [PATCH 5/7] add GPMI support for imx28

[Jason Liu]

2011/3/24 Lothar Waßmann <LW@karo-electronics.de>:
> Hi,
[...]
>> Most of the time, the timing is really based on a safe timing setting.
>> But in the original GPMI driver in the FREESCALE BSP, there exits some
>> nands need to be set with their own timing setting.
>>
>> So I do not use the safe timing for _ALL_ the nand, and i'd better get
>> it from the
>> database.
>>
> It should be sufficient to provide timing info from platform_data in
> special cases instead of bloating the nand id database with that
> stuff. Platforms might need to adjust the timing because of
> peculiarities in the HW. Thus the timing info should be provided from
> there, not from the chip database.

No, we can't. since some boards only provide one NAND socket, customer
can place any NAND flash chip they want. And with the NAND tech evolution, some
NAND flash will end-of-line and customer need change another new NAND.
As we all know that RAW NAND flash vendor does not follow the same
rule to encode
ID related information such as page size/oob size/block size etc. Even
with same vendor,
take Sumsung as example, there is not one generic rule to encode the
id information.
If you do NAND support with many customers, you will find that
currenly linux NAND driver
(nand_base.c/nand_ids.c) provide very poor support for that.

Jason

>
>
> Lothar Waßmann
> --
> ___________________________________________________________
>
> Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
> Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
> Geschäftsführer: Matthias Kaussen
> Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
>
> www.karo-electronics.de | info@karo-electronics.de
> ___________________________________________________________
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

Re: [PATCH 5/7] add GPMI support for imx28

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 415 bytes --]


> If you do NAND support with many customers, you will find that
> currenly linux NAND driver
> (nand_base.c/nand_ids.c) provide very poor support for that.

Then what about improving that instead of doing a private layer?

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]

Re: [PATCH 5/7] add GPMI support for imx28

[Lothar Waßmann]

Hi,

Jason Liu writes:
> 2011/3/24 Lothar Waßmann <LW@karo-electronics.de>:
> > Hi,
> [...]
> >> Most of the time, the timing is really based on a safe timing setting.
> >> But in the original GPMI driver in the FREESCALE BSP, there exits some
> >> nands need to be set with their own timing setting.
> >>
> >> So I do not use the safe timing for _ALL_ the nand, and i'd better get
> >> it from the
> >> database.
> >>
> > It should be sufficient to provide timing info from platform_data in
> > special cases instead of bloating the nand id database with that
> > stuff. Platforms might need to adjust the timing because of
> > peculiarities in the HW. Thus the timing info should be provided from
> > there, not from the chip database.
> 
> No, we can't. since some boards only provide one NAND socket, customer
> can place any NAND flash chip they want. And with the NAND tech evolution, some
> NAND flash will end-of-line and customer need change another new NAND.
> As we all know that RAW NAND flash vendor does not follow the same
> rule to encode
> ID related information such as page size/oob size/block size etc. Even
> with same vendor,
> take Sumsung as example, there is not one generic rule to encode the
> id information.
> If you do NAND support with many customers, you will find that
> currenly linux NAND driver
> (nand_base.c/nand_ids.c) provide very poor support for that.
> 
That's a reason to improve that support, not to invent private fixes
for each chip driver.


Lothar Waßmann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________

Re: [PATCH 5/7] add GPMI support for imx28

[Huang Shijie]

Hi Lothar:

> Hi,
>
> Huang Shijie writes:
>> Hi Lothar:
>>>>> some general comments:
>>>>> - Why are you not using the existing nand_ids but inventing your own
>>>>>      database?
>>>>>
>>>> The nand_ids{} contains poor information for me.
>>>> Such as :
>>>> [1]The nand_ids does not have the enough information for the page
>>>> size,oob size for some new NANDs.
>>>>       And you can not get the information from parsing the NAND ids, such
>>>> as some Micron NANDs.
>>>>
>>> You could use it for the standard chips where you do not need
>>> additional information. That way most NAND chips could be supported
>>> out of the box without having to modify the driver.
>>>
>> What the meaning of "standard chips"?
>>
> Those chips that are supported by other drivers for long time.
>
see belowing.
>> There are many nands in the world. Every vendor has its own rules, some
>> even does has :)
>>
>> Unluckily, the imx23/imx28 supports many nands that the nand_ids{} does
>> not support.
>>
> That's no reason to scrap support for all chips that every other
> driver supports.
>
Frankly speaking, Which nand we should to support depends on the 
customer's requires.

So we really do not want to support other nands that the customer does 
not have.

>> I have many nands by my hand. I will add it gradually.
>>
> So why not add them to the generic database?
>
I ever thought to change the generic database. But I found it would cost 
a long time.

The parsing code in nand_get_flash_type() can not parse out the page 
size/oob size
in some cases. And IMHO I do not think to get the page size/oob size by 
parsing the ids is a good way,
this really makes the code mess (sorry, David, I really think the 
current code is ugly.).

IMHO, the best solution is add a database like mine. Using the id bytes 
as the keyword to match the nand.
then to get the page size /oob size , etc, from the database.

I will send a patch about this in future, but now, I do not want to  be 
stumbled by this problem.




>> I want to get the page size/oob size from my own database which can not
>> get from the nand_ids.
>>
> If there are parameters needed that cannot be obtained from the
> generic database, it might be worth upgrading that database instead of
> creating your own local database.
>
>>>> [2]I need the timing information of the NAND. The nand_ids DOES not have
>>>> it. I have to
>>>>       read the datasheet of the NAND, and add it to my database.
>>>>
>>> Do we really need exact timing data for each individual chip?
>>> Or couldn't we live with some sane timing that works for most chips
>>> and provide some means to specify a different timing via
>>> platform_data?
>>>
>> Most of the time, the timing is really based on a safe timing setting.
>> But in the original GPMI driver in the FREESCALE BSP, there exits some
>> nands need to be set with their own timing setting.
>>
>> So I do not use the safe timing for _ALL_ the nand, and i'd better get
>> it from the
>> database.
>>
> It should be sufficient to provide timing info from platform_data in
> special cases instead of bloating the nand id database with that
> stuff. Platforms might need to adjust the timing because of
> peculiarities in the HW. Thus the timing info should be provided from
> there, not from the chip database.

The timing information is needed by the GPMI module, not other module. 
So the
best way to get this is from the chip database.

Setting the GPMI with the proper timing will make the NAND runs in high 
performance.

Thanks for your advice, I will use the safe timing for all the nand.

Huang Shijie

Re: [PATCH 5/7] add GPMI support for imx28

[Florian Fainelli]

Hello Huang,

On Thursday 24 March 2011 09:51:40 Huang Shijie wrote:
> Hi Lothar:
> > Hi,
> > 
> > Huang Shijie writes:
> >> Hi Lothar:
> >>>>> some general comments:
> >>>>> - Why are you not using the existing nand_ids but inventing your own
> >>>>> 
> >>>>>      database?
> >>>> 
> >>>> The nand_ids{} contains poor information for me.
> >>>> Such as :
> >>>> [1]The nand_ids does not have the enough information for the page
> >>>> size,oob size for some new NANDs.
> >>>> 
> >>>>       And you can not get the information from parsing the NAND ids,
> >>>>       such
> >>>> 
> >>>> as some Micron NANDs.
> >>> 
> >>> You could use it for the standard chips where you do not need
> >>> additional information. That way most NAND chips could be supported
> >>> out of the box without having to modify the driver.
> >> 
> >> What the meaning of "standard chips"?
> > 
> > Those chips that are supported by other drivers for long time.
> 
> see belowing.
> 
> >> There are many nands in the world. Every vendor has its own rules, some
> >> even does has :)
> >> 
> >> Unluckily, the imx23/imx28 supports many nands that the nand_ids{} does
> >> not support.
> > 
> > That's no reason to scrap support for all chips that every other
> > driver supports.
> 
> Frankly speaking, Which nand we should to support depends on the
> customer's requires.
> 
> So we really do not want to support other nands that the customer does
> not have.
> 
> >> I have many nands by my hand. I will add it gradually.
> > 
> > So why not add them to the generic database?
> 
> I ever thought to change the generic database. But I found it would cost
> a long time.
> 
> The parsing code in nand_get_flash_type() can not parse out the page
> size/oob size
> in some cases. And IMHO I do not think to get the page size/oob size by
> parsing the ids is a good way,
> this really makes the code mess (sorry, David, I really think the
> current code is ugly.).
> 
> IMHO, the best solution is add a database like mine. Using the id bytes
> as the keyword to match the nand.
> then to get the page size /oob size , etc, from the database.
> 
> I will send a patch about this in future, but now, I do not want to  be
> stumbled by this problem.
> 
> >> I want to get the page size/oob size from my own database which can not
> >> get from the nand_ids.
> > 
> > If there are parameters needed that cannot be obtained from the
> > generic database, it might be worth upgrading that database instead of
> > creating your own local database.
> > 
> >>>> [2]I need the timing information of the NAND. The nand_ids DOES not
> >>>> have it. I have to
> >>>> 
> >>>>       read the datasheet of the NAND, and add it to my database.
> >>> 
> >>> Do we really need exact timing data for each individual chip?
> >>> Or couldn't we live with some sane timing that works for most chips
> >>> and provide some means to specify a different timing via
> >>> platform_data?
> >> 
> >> Most of the time, the timing is really based on a safe timing setting.
> >> But in the original GPMI driver in the FREESCALE BSP, there exits some
> >> nands need to be set with their own timing setting.
> >> 
> >> So I do not use the safe timing for _ALL_ the nand, and i'd better get
> >> it from the
> >> database.
> > 
> > It should be sufficient to provide timing info from platform_data in
> > special cases instead of bloating the nand id database with that
> > stuff. Platforms might need to adjust the timing because of
> > peculiarities in the HW. Thus the timing info should be provided from
> > there, not from the chip database.
> 
> The timing information is needed by the GPMI module, not other module.
> So the
> best way to get this is from the chip database.

Such a database already exists in drivers/mtd/nand/nand_ids.c. The idea here 
would be for you to get the NAND geometry characteristics from nands_ids.c, 
which benefits to all drivers in general, and let platform code define specific 
timings, which is specific to your driver.

> 
> Setting the GPMI with the proper timing will make the NAND runs in high
> performance.
> 
> Thanks for your advice, I will use the safe timing for all the nand.

If platform code does not define any timings, then yes, use the safest timings 
possible, if provided, let the platform configure its timings.
--
Florian

Re: [PATCH 5/7] add GPMI support for imx28

[Huang Shijie]

Hi Florian:


> Hello Huang,
>
> On Thursday 24 March 2011 09:51:40 Huang Shijie wrote:
>> Hi Lothar:
>>> Hi,
>>>
>>> Huang Shijie writes:
>>>> Hi Lothar:
>>>>>>> some general comments:
>>>>>>> - Why are you not using the existing nand_ids but inventing your own
>>>>>>>
>>>>>>>       database?
>>>>>> The nand_ids{} contains poor information for me.
>>>>>> Such as :
>>>>>> [1]The nand_ids does not have the enough information for the page
>>>>>> size,oob size for some new NANDs.
>>>>>>
>>>>>>        And you can not get the information from parsing the NAND ids,
>>>>>>        such
>>>>>>
>>>>>> as some Micron NANDs.
>>>>> You could use it for the standard chips where you do not need
>>>>> additional information. That way most NAND chips could be supported
>>>>> out of the box without having to modify the driver.
>>>> What the meaning of "standard chips"?
>>> Those chips that are supported by other drivers for long time.
>> see belowing.
>>
>>>> There are many nands in the world. Every vendor has its own rules, some
>>>> even does has :)
>>>>
>>>> Unluckily, the imx23/imx28 supports many nands that the nand_ids{} does
>>>> not support.
>>> That's no reason to scrap support for all chips that every other
>>> driver supports.
>> Frankly speaking, Which nand we should to support depends on the
>> customer's requires.
>>
>> So we really do not want to support other nands that the customer does
>> not have.
>>
>>>> I have many nands by my hand. I will add it gradually.
>>> So why not add them to the generic database?
>> I ever thought to change the generic database. But I found it would cost
>> a long time.
>>
>> The parsing code in nand_get_flash_type() can not parse out the page
>> size/oob size
>> in some cases. And IMHO I do not think to get the page size/oob size by
>> parsing the ids is a good way,
>> this really makes the code mess (sorry, David, I really think the
>> current code is ugly.).
>>
>> IMHO, the best solution is add a database like mine. Using the id bytes
>> as the keyword to match the nand.
>> then to get the page size /oob size , etc, from the database.
>>
>> I will send a patch about this in future, but now, I do not want to  be
>> stumbled by this problem.
>>
>>>> I want to get the page size/oob size from my own database which can not
>>>> get from the nand_ids.
>>> If there are parameters needed that cannot be obtained from the
>>> generic database, it might be worth upgrading that database instead of
>>> creating your own local database.
>>>
>>>>>> [2]I need the timing information of the NAND. The nand_ids DOES not
>>>>>> have it. I have to
>>>>>>
>>>>>>        read the datasheet of the NAND, and add it to my database.
>>>>> Do we really need exact timing data for each individual chip?
>>>>> Or couldn't we live with some sane timing that works for most chips
>>>>> and provide some means to specify a different timing via
>>>>> platform_data?
>>>> Most of the time, the timing is really based on a safe timing setting.
>>>> But in the original GPMI driver in the FREESCALE BSP, there exits some
>>>> nands need to be set with their own timing setting.
>>>>
>>>> So I do not use the safe timing for _ALL_ the nand, and i'd better get
>>>> it from the
>>>> database.
>>> It should be sufficient to provide timing info from platform_data in
>>> special cases instead of bloating the nand id database with that
>>> stuff. Platforms might need to adjust the timing because of
>>> peculiarities in the HW. Thus the timing info should be provided from
>>> there, not from the chip database.
>> The timing information is needed by the GPMI module, not other module.
>> So the
>> best way to get this is from the chip database.
> Such a database already exists in drivers/mtd/nand/nand_ids.c. The idea here
> would be for you to get the NAND geometry characteristics from nands_ids.c,
> which benefits to all drivers in general, and let platform code define specific
> timings, which is specific to your driver.
>
I will remove the timing fields.

thanks.

Re: [PATCH 2/7] add the common code for GPMI driver

[Huang Shijie]

Hi:

>> +
>> +static int acquire_register_block(struct gpmi_nfc_data *this,
>> +			const char *resource_name, void **reg_block_base)
>> +{
>> +	struct platform_device  *pdev = this->pdev;
>> +	struct resource         *r;
>> +	void                    *p;
>> +
>> +	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, resource_name);
>> +	if (!r) {
>> +		log("Can't get resource information for '%s'", resource_name);
>> +		return -ENXIO;
>> +	}
>> +
>> +	/* remap the register block */
>> +	p = ioremap(r->start, r->end - r->start + 1);
>                                ^^^^^^^^^^^^^^^^^^^^^
> resource_size(r)
>
thanks.

>
>> +static int acquire_interrupt(struct gpmi_nfc_data *this,
>> +			const char *resource_name,
>> +			irq_handler_t interrupt_handler, int *lno, int *hno)
>> +{
>> +	struct platform_device  *pdev = this->pdev;
>> +	struct resource         *r;
>> +	int                     err = 0;
>>
> Useless initialization.
>
ok.
>> +	r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, resource_name);
>> +	if (!r) {
>> +		log("Can't get resource information for '%s'", resource_name);
>> +		return -ENXIO;
>> +	}
>> +
>> +	BUG_ON(r->start != r->end);
>> +	err = request_irq(r->start, interrupt_handler, 0, resource_name, this);
>> +	if (err) {
>> +		log("Can't own %s", resource_name);
>> +		return -EIO;
>>
> Promote the error code from request_irq().
>
thanks.
>> +	}
>> +
>> +	*lno = r->start;
>> +	*hno = r->end;
>> +	return 0;
>> +}
>> +
>> +static void release_interrupt(struct gpmi_nfc_data *this,
>> +			int low_interrupt_number, int high_interrupt_number)
>> +{
>> +	int i;
>> +	for (i = low_interrupt_number; i<= high_interrupt_number; i++)
>> +		free_irq(i, this);
>> +}
>> +
>>
>> +
>> +static void release_dma_channels(struct gpmi_nfc_data *this)
>> +{
>> +	unsigned int   i;
>> +	for (i = 0; i<= DMA_CHANS; i++)
>>
> Obiwan error! should be 'i<  DMA_CHANS'
>
  thanks a lot!
>> +		if (this->dma_chans[i]) {
>> +			dma_release_channel(this->dma_chans[i]);
>> +			this->dma_chans[i] = NULL;
>> +		}
>> +}
>> +
>>
>> +static inline int acquire_clock(struct gpmi_nfc_data *this,
>> +			const char *clock_name, struct clk **clock)
>> +{
>> +	struct clk *c;
>> +
>> +	c = clk_get(this->dev, clock_name);
>> +	if (IS_ERR(c)) {
>> +		log("Can't own clock %s", clock_name);
>> +		return PTR_ERR(c);
>> +	}
>> +	*clock = c;
>> +	return 0;
>> +}
>> +
>> +static void release_clock(struct gpmi_nfc_data *this, struct clk *clock)
>> +{
>> +	clk_disable(clock);
>>
> Unbalanced clk_disable().
thanks.
>> +	clk_put(clock);
>> +}
>> +
>> +static int acquire_resources(struct gpmi_nfc_data *this)
>> +{
>> +	struct gpmi_nfc_platform_data  *pdata     =  this->pdata;
>> +	struct resources               *resources =&this->resources;
>> +	int                            error      = 0;
>>
> Useless initialization.
ok.
>> +
>> +	/* Attempt to acquire our clock. */
>> +	error = acquire_clock(this, pdata->clock_name,&resources->clock);
>>
> Abuse of the clock API. Don't pass clock names via platform_data.
>
thanks, I will change it in next version.
>> +static int set_up_nfc_hal(struct gpmi_nfc_data *this)
>> +{
>> +	struct gpmi_nfc_platform_data  *pdata = this->pdata;
>> +	struct nfc_hal                 *nfc;
>> +	int                            error = 0;
>>
> Useless initialization.
>
>> +	/*
>> +	 * This structure contains the "safe" GPMI timing that should succeed
>> +	 * with any NAND Flash device
>> +	 * (although, with less-than-optimal performance).
>> +	 */
>> +	static struct nand_timing  safe_timing = {
>> +		.data_setup_in_ns        = 80,
>> +		.data_hold_in_ns         = 60,
>> +		.address_setup_in_ns     = 25,
>> +		.gpmi_sample_delay_in_ns =  6,
>> +		.tREA_in_ns              = -1,
>> +		.tRLOH_in_ns             = -1,
>> +		.tRHOH_in_ns             = -1,
>> +	};
>> +
>> +	switch (pdata->chip_version) {
>> +	case CHIP_VERSION_IMX23:
>> +		nfc =&gpmi_nfc_hal_imx23;
>> +		break;
>> +	case CHIP_VERSION_IMX28:
>> +		nfc =&gpmi_nfc_hal_imx28;
>> +		break;
>> +	default:
>> +		log("Unkown NFC version %u", pdata->chip_version);
>> +		return -ENXIO;
>> +	}
>>
> Use platform_ids to distinguish between HW variants.
>
ok.
>> +
>> +	this->nfc = nfc;
>> +
>> +	/* Initialize the NFC HAL. */
>> +	error = nfc->init(this);
>> +	if (error)
>> +		return error;
>> +
>> +	/* Set up safe timing. */
>> +	nfc->set_timing(this,&safe_timing);
>> +	return 0;
>> +}
>> +
>> +static int set_up_boot_rom_helper(struct gpmi_nfc_data *this)
>> +{
>> +	struct gpmi_nfc_platform_data  *pdata = this->pdata;
>> +	struct boot_rom_helper         *rom;
>> +
>> +	switch (pdata->chip_version) {
>> +	case CHIP_VERSION_IMX23:
>> +		rom =&gpmi_nfc_boot_rom_imx23;
>> +		break;
>> +	case CHIP_VERSION_IMX28:
>> +		rom =&gpmi_nfc_boot_rom_imx28;
>> +		break;
>> +	default:
>> +		log("Unkown NFC version %u", pdata->chip_version);
>> +		return -ENXIO;
>> +	}
>> +
>> +	pr_info("Boot ROM: Version %u, %s\n", rom->version, rom->description);
>> +	this->rom = rom;
>> +	return 0;
>> +}
>> +
>> +/* Creates/Removes sysfs files for this device.*/
>> +static void manage_sysfs_files(struct gpmi_nfc_data *this, int create)
>> +{
>> +	struct device            *dev = this->dev;
>> +	int                      error;
>> +	unsigned int             i;
>> +	struct device_attribute  **attr;
>> +
>> +	for (i = 0, attr = device_attributes;
>> +			i<  ARRAY_SIZE(device_attributes); i++, attr++) {
>> +
>> +		if (create) {
>> +			error = device_create_file(dev, *attr);
>> +			if (error) {
>> +				while (--attr>= device_attributes)
>> +					device_remove_file(dev, *attr);
>> +				return;
>> +			}
>> +		} else {
>> +			device_remove_file(dev, *attr);
>> +		}
>> +	}
>> +}
>> +
>> +static int gpmi_nfc_probe(struct platform_device *pdev)
>> +{
>> +	struct gpmi_nfc_platform_data  *pdata = pdev->dev.platform_data;
>> +	struct gpmi_nfc_data           *this  = 0;
>> +	int                            error  = 0;
>>
> Useless initialization (NB: pointers are initialized with 'NULL' not
> '0').
>
thanks.

I have already changed a lot, but i missed this one.
>> +/* This structure represents this driver to the platform management system. */
>> +static struct platform_driver gpmi_nfc_driver = {
>> +	.driver = {
>> +		.name = GPMI_NFC_DRIVER_NAME,
>> +	},
>> +	.probe   = gpmi_nfc_probe,
>> +	.remove  = __exit_p(gpmi_nfc_remove),
>> +	.suspend = gpmi_nfc_suspend,
>> +	.resume  = gpmi_nfc_resume,
>> +};
>> +
>> +static int __init gpmi_nfc_init(void)
>> +{
>> +	printk(KERN_INFO "GPMI NFC driver registered. (IMX)\n");
>> +	if (platform_driver_register(&gpmi_nfc_driver) != 0) {
>> +		pr_err("i.MX GPMI NFC driver registration failed\n");
>> +		return -ENODEV;
>>
> Promote the error code from platform_driver_register().
>
ok
>> +	}
>> +	return 0;
>> +}
>> +
>> +static void __exit gpmi_nfc_exit(void)
>> +{
>> +	platform_driver_unregister(&gpmi_nfc_driver);
>> +}
>> +
>> +module_init(gpmi_nfc_init);
>> +module_exit(gpmi_nfc_exit);
>> +
>> +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
>> +MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver");
>> +MODULE_LICENSE("GPL");
>> diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
>> new file mode 100644
>> index 0000000..b5a2d77
>> --- /dev/null
>> +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
>> @@ -0,0 +1,520 @@
>> +/*
>> + * Freescale GPMI NFC NAND Flash Driver
>> + *
>> + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
>> + * Copyright (C) 2008 Embedded Alley Solutions, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, write to the Free Software Foundation, Inc.,
>> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
>> + */
>> +
>> +#ifndef __DRIVERS_MTD_NAND_GPMI_NFC_H
>> +#define __DRIVERS_MTD_NAND_GPMI_NFC_H
>> +
>> +/* Linux header files. */
>> +#include<linux/err.h>
>> +#include<linux/init.h>
>> +#include<linux/module.h>
>> +#include<linux/io.h>
>> +#include<linux/interrupt.h>
>> +#include<linux/clk.h>
>> +#include<linux/delay.h>
>> +#include<linux/platform_device.h>
>> +#include<linux/dma-mapping.h>
>> +#include<linux/mtd/mtd.h>
>> +#include<linux/mtd/nand.h>
>> +#include<linux/mtd/partitions.h>
>> +#include<linux/mtd/concat.h>
>> +#include<linux/dmaengine.h>
>> +#include<asm/sizes.h>
>> +
>> +/* Platform header files. */
>> +#include<mach/mxs.h>
>> +#include<mach/common.h>
>> +#include<mach/dma.h>
>> +#include<mach/gpmi-nfc.h>
>> +#include<mach/system.h>
>> +#include<mach/clock.h>
>> +
>> +/* Driver header files. */
>> +#include "nand_device_info.h"
>> +
>> +/*
>> + *------------------------------------------------------------------------------
>> + * Fundamental Data Structures
>> + *------------------------------------------------------------------------------
>> + */
>> +
>> +/**
>> + * struct resources - The collection of resources the driver needs.
>> + *
>> + * @gpmi_regs:         A pointer to the GPMI registers.
>> + * @bch_regs:          A pointer to the BCH registers.
>> + * @bch_interrupt:     The BCH interrupt number.
>> + * @dma_low_channel:   The low  DMA channel.
>> + * @dma_high_channel:  The high DMA channel.
>> + * @clock:             A pointer to the struct clk for the NFC's clock.
>> + */
>> +struct resources {
>> +	void          *gpmi_regs;
>> +	void          *bch_regs;
>> +	unsigned int  bch_low_interrupt;
>> +	unsigned int  bch_high_interrupt;
>> +	unsigned int  dma_low_channel;
>> +	unsigned int  dma_high_channel;
>> +	struct clk    *clock;
>> +};
>> +
>> +/**
>> + * struct mil - State for the MTD Interface Layer.
>> + *
>> + * @nand:                    The NAND Flash MTD data structure that represents
>> + *                           the NAND Flash medium.
>> + * @mtd:                     The MTD data structure that represents the NAND
>> + *                           Flash medium.
>> + * @oob_layout:              A structure that describes how bytes are laid out
>> + *                           in the OOB.
>> + * @general_use_mtd:         A pointer to an MTD we export for general use.
>> + *                           This *may* simply be a pointer to the mtd field, if
>> + *                           we've been instructed NOT to protect the boot
>> + *                           areas.
>> + * @partitions:              A pointer to a set of partitions applied to the
>> + *                           general use MTD.
>> + * @partition_count:         The number of partitions.
>> + * @current_chip:            The chip currently selected by the NAND Fash MTD
>> + *                           code. A negative value indicates that no chip is
>> + *                           selected.
>> + * @command_length:          The length of the command that appears in the
>> + *                           command buffer (see cmd_virt, below).
>> + * @ignore_bad_block_marks:  Indicates we are ignoring bad block marks.
>> + * @saved_bbt:               A saved pointer to the in-memory NAND Flash MTD bad
>> + *                           block table. See show_device_ignorebad() for more
>> + *                           details.
>> + * @marking_a_bad_block:     Indicates the caller is marking a bad block. See
>> + *                           mil_ecc_write_oob() for details.
>> + * @hooked_block_markbad:    A pointer to the block_markbad() function we
>> + *                           we "hooked." See mil_ecc_write_oob() for details.
>> + * @upper_buf:               The buffer passed from upper layer.
>> + * @upper_len:               The buffer len passed from upper layer.
>> + * @direct_dma_map_ok:       Is the direct DMA map is good for the upper_buf?
>> + * @cmd_sgl/cmd_buffer:      For NAND command.
>> + * @data_sgl/data_buffer_dma:For NAND DATA ops.
>> + * @page_buffer_virt:        A pointer to a DMA-coherent buffer we use for
>> + *                           reading and writing pages. This buffer includes
>> + *                           space for both the payload data and the auxiliary
>> + *                           data (including status bytes, but not syndrome
>> + *                           bytes).
>> + * @page_buffer_phys:        The physical address for the page_buffer_virt
>> + *                           buffer.
>> + * @page_buffer_size:        The size of the page buffer.
>> + * @payload_virt:            A pointer to a location in the page buffer used
>> + *                           for payload bytes. The size of this buffer is
>> + *                           determined by struct nfc_geometry.
>> + * @payload_phys:            The physical address for payload_virt.
>> + * @auxiliary_virt:          A pointer to a location in the page buffer used
>> + *                           for auxiliary bytes. The size of this buffer is
>> + *                           determined by struct nfc_geometry.
>> + * @auxiliary_phys:          The physical address for auxiliary_virt.
>> + */
>> +struct mil {
>> +	/* MTD Data Structures */
>> +	struct nand_chip       nand;
>> +	struct mtd_info        mtd;
>> +	struct nand_ecclayout  oob_layout;
>> +
>> +	/* Partitioning and Boot Area Protection */
>> +	struct mtd_info        *general_use_mtd;
>> +	struct mtd_partition   *partitions;
>> +	unsigned int           partition_count;
>> +
>> +	/* General-use Variables */
>> +	int                    current_chip;
>> +	unsigned int           command_length;
>> +	int                    ignore_bad_block_marks;
>> +	void                   *saved_bbt;
>> +
>> +	/* MTD Function Pointer Hooks */
>> +	int                    marking_a_bad_block;
>> +	int                    (*hooked_block_markbad)(struct mtd_info *mtd,
>> +					loff_t ofs);
>> +
>> +	/* from upper layer */
>> +	uint8_t			*upper_buf;
>> +	int			upper_len;
>> +
>> +	/* DMA */
>> +	bool			direct_dma_map_ok;
>> +
>> +	struct scatterlist	cmd_sgl;
>> +	char			*cmd_buffer;
>> +
>> +	struct scatterlist	data_sgl;
>> +	char			*data_buffer_dma;
>> +
>> +	void                   *page_buffer_virt;
>> +	dma_addr_t             page_buffer_phys;
>> +	unsigned int           page_buffer_size;
>> +
>> +	void                   *payload_virt;
>> +	dma_addr_t             payload_phys;
>> +
>> +	void                   *auxiliary_virt;
>> +	dma_addr_t             auxiliary_phys;
>> +};
>>
> IMO this struct should be removed and the members integrated into the
> struct gpmi_nfc_data.
>
>> +
>> +/**
>> + * struct nfc_geometry - NFC geometry description.
>> + *
>> + * This structure describes the NFC's view of the medium geometry.
>> + *
>> + * @ecc_algorithm:            The human-readable name of the ECC algorithm
>> + *                            (e.g., "Reed-Solomon" or "BCH").
>> + * @ecc_strength:             A number that describes the strength of the ECC
>> + *                            algorithm.
>> + * @page_size_in_bytes:       The size, in bytes, of a physical page, including
>> + *                            both data and OOB.
>> + * @metadata_size_in_bytes:   The size, in bytes, of the metadata.
>> + * @ecc_chunk_size_in_bytes:  The size, in bytes, of a single ECC chunk. Note
>> + *                            the first chunk in the page includes both data and
>> + *                            metadata, so it's a bit larger than this value.
>> + * @ecc_chunk_count:          The number of ECC chunks in the page,
>> + * @payload_size_in_bytes:    The size, in bytes, of the payload buffer.
>> + * @auxiliary_size_in_bytes:  The size, in bytes, of the auxiliary buffer.
>> + * @auxiliary_status_offset:  The offset into the auxiliary buffer at which
>> + *                            the ECC status appears.
>> + * @block_mark_byte_offset:   The byte offset in the ECC-based page view at
>> + *                            which the underlying physical block mark appears.
>> + * @block_mark_bit_offset:    The bit offset into the ECC-based page view at
>> + *                            which the underlying physical block mark appears.
>> + */
>> +struct nfc_geometry {
>> +	char          *ecc_algorithm;
>> +	unsigned int  ecc_strength;
>> +	unsigned int  page_size_in_bytes;
>> +	unsigned int  metadata_size_in_bytes;
>> +	unsigned int  ecc_chunk_size_in_bytes;
>> +	unsigned int  ecc_chunk_count;
>> +	unsigned int  payload_size_in_bytes;
>> +	unsigned int  auxiliary_size_in_bytes;
>> +	unsigned int  auxiliary_status_offset;
>> +	unsigned int  block_mark_byte_offset;
>> +	unsigned int  block_mark_bit_offset;
>> +};
> Most of these parameters are already available in the mtd_info
> structure. No need to duplicate them here!
I will remove some ones.
>> +
>> +/**
>> + * struct boot_rom_geometry - Boot ROM geometry description.
>> + *
>> + * This structure encapsulates decisions made by the Boot ROM Helper.
>> + *
>> + * @boot_area_count:             The number of boot areas. The first boot area
>> + *                               appears at the beginning of chip 0, the next
>> + *                               at the beginning of chip 1, etc.
>> + * @boot_area_size_in_bytes:     The size, in bytes, of each boot area.
>> + * @stride_size_in_pages:        The size of a boot block stride, in pages.
>> + * @search_area_stride_exponent: The logarithm to base 2 of the size of a
>> + *                               search area in boot block strides.
>> + */
>> +struct boot_rom_geometry {
>> +	unsigned int  boot_area_count;
>> +	unsigned int  boot_area_size_in_bytes;
>> +	unsigned int  stride_size_in_pages;
>> +	unsigned int  search_area_stride_exponent;
>> +};
>>
> IMO the whole boot_rom stuff should not be part of an mtd chip driver,
> but has its place in the mtd partition handlers.
>
I have explained this in preview email. thanks
>> +/* Can we use the upper's buffer directly for DMA? */
>> +void prepare_data_dma(struct gpmi_nfc_data *this, enum dma_data_direction dr)
>> +{
>> +	struct mil *mil =&this->mil;
>> +	struct scatterlist *sgl =&mil->data_sgl;
>> +	int ret = 0;
>> +
>> +	mil->direct_dma_map_ok = true;
>> +
>> +	/* first try to map the upper buffer directly */
>> +	sg_init_one(sgl, mil->upper_buf, mil->upper_len);
>> +	ret = dma_map_sg(this->dev, sgl, 1, dr);
>> +	if (ret == 0) {
>> +		/* We have to use our own DMA buffer. */
>> +		sg_init_one(sgl, mil->data_buffer_dma, PAGE_SIZE);
>> +		ret = dma_map_sg(this->dev, sgl, 1, dr);
>> +		BUG_ON(ret == 0);
>> +
>> +		if (dr == DMA_TO_DEVICE)
>> +			memcpy(mil->data_buffer_dma, mil->upper_buf,
>> +				mil->upper_len);
>> +		mil->direct_dma_map_ok = false;
>> +	}
>> +	sgl->length = mil->upper_len;
>>
> This has already been done by sg_init_one().
>
thanks.
>> +}
>> +
>> +/* This will be called after the DMA operation is finished. */
>> +static void dma_irq_callback(void *param)
>> +{
>> +	struct gpmi_nfc_data *this = param;
>> +	struct nfc_hal *nfc = this->nfc;
>> +	struct mil *mil =&this->mil;
>> +
>> +	complete(&nfc->dma_done);
>> +
>> +	switch (this->dma_type) {
>> +	case DMA_FOR_COMMAND:
>> +		dma_unmap_sg(this->dev,&mil->cmd_sgl, 1, DMA_TO_DEVICE);
>> +		break;
>> +
>> +	case DMA_FOR_READ_DATA:
>> +		if (mil->direct_dma_map_ok == false)
>> +			memcpy(mil->upper_buf, (char *)mil->data_buffer_dma,
>> +				mil->upper_len);
>> +		dma_unmap_sg(this->dev,&mil->data_sgl, 1, DMA_FROM_DEVICE);
>> +		break;
>> +
>> +	case DMA_FOR_WRITE_DATA:
>> +		dma_unmap_sg(this->dev,&mil->data_sgl, 1, DMA_TO_DEVICE);
>> +		break;
>> +
>> +	case DMA_FOR_READ_ECC_PAGE:
>> +	case DMA_FOR_WRITE_ECC_PAGE:
>> +		break;
>> +
>> +	default:
>> +		BUG();
>> +	}
>> +}
>> +
>>
>> +static uint8_t mil_read_byte(struct mtd_info *mtd)
>> +{
>> +	uint8_t  byte = 0;
>> +	mil_read_buf(mtd, (uint8_t *)&byte, 1);
>>
> With CONFIG_DMA_API_DEBUG enabled this would blow up right in your
> face:
> |gpmi-nfc gpmi-nfc: DMA-API: device driver maps memory fromstack [addr=c732bd3f]
>
Thanks a lot.
>> +	return byte;
>> +}
>> +
>> +/**
>> + * mil_handle_block_mark_swapping() - Handles block mark swapping.
>> + *
>> + * Note that, when this function is called, it doesn't know whether it's
>> + * swapping the block mark, or swapping it *back* -- but it doesn't matter
>> + * because the the operation is the same.
>> + *
>> + * @this:       Per-device data.
>> + * @payload:    A pointer to the payload buffer.
>> + * @auxiliary:  A pointer to the auxiliary buffer.
>> + */
>> +static void mil_handle_block_mark_swapping(struct gpmi_nfc_data *this,
>> +						void *payload, void *auxiliary)
>> +{
>> +	struct nfc_geometry     *nfc_geo =&this->nfc_geometry;
>> +	struct boot_rom_helper  *rom     =  this->rom;
>> +	unsigned char           *p;
>> +	unsigned char           *a;
>> +	unsigned int            bit;
>> +	unsigned char           mask;
>> +	unsigned char           from_data;
>> +	unsigned char           from_oob;
>> +
>> +	/* Check if we're doing block mark swapping. */
>> +	if (!rom->swap_block_mark)
>> +		return;
>> +
>> +	/*
>> +	 * If control arrives here, we're swapping. Make some convenience
>> +	 * variables.
>> +	 */
>> +	bit = nfc_geo->block_mark_bit_offset;
>> +	p   = ((unsigned char *) payload) + nfc_geo->block_mark_byte_offset;
>>
> Useless cast.
ok.
>> +	a   = auxiliary;
>> +
>> +	/*
>> +	 * Get the byte from the data area that overlays the block mark. Since
>> +	 * the ECC engine applies its own view to the bits in the page, the
>> +	 * physical block mark won't (in general) appear on a byte boundary in
>> +	 * the data.
>> +	 */
>> +	from_data = (p[0]>>  bit) | (p[1]<<  (8 - bit));
>> +
>> +	/* Get the byte from the OOB. */
>> +	from_oob = a[0];
>> +
>> +	/* Swap them. */
>> +	a[0] = from_data;
>> +
>> +	mask = (0x1<<  bit) - 1;
>> +	p[0] = (p[0]&  mask) | (from_oob<<  bit);
>> +
>> +	mask = ~0<<  bit;
>> +	p[1] = (p[1]&  mask) | (from_oob>>  (8 - bit));
>> +}
>> +
>> +static int mil_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
>> +				uint8_t *buf, int page)
>> +{
>> +	struct gpmi_nfc_data    *this    = nand->priv;
>> +	struct nfc_hal          *nfc     =  this->nfc;
>> +	struct nfc_geometry     *nfc_geo =&this->nfc_geometry;
>> +	struct mil              *mil     =&this->mil;
>> +	void                    *payload_virt   =  0;
>> +	dma_addr_t              payload_phys    = ~0;
>> +	void                    *auxiliary_virt =  0;
>> +	dma_addr_t              auxiliary_phys  = ~0;
> Useless initialization.
>
ok.
>> +	unsigned int            i;
>> +	unsigned char           *status;
>> +	unsigned int            failed;
>> +	unsigned int            corrected;
>> +	int                     error = 0;
>> +
> Dto.
>
>> +	error = read_page_prepare(this, buf, mtd->writesize,
>> +					mil->payload_virt, mil->payload_phys,
>> +					nfc_geo->payload_size_in_bytes,
>> +					&payload_virt,&payload_phys);
>> +	if (error) {
>> +		log("Inadequate DMA buffer");
>> +		error = -ENOMEM;
>> +		return error;
>> +	}
>> +	auxiliary_virt = mil->auxiliary_virt;
>> +	auxiliary_phys = mil->auxiliary_phys;
>> +
>> +	/* ask the NFC */
>> +	error = nfc->read_page(this, payload_phys, auxiliary_phys);
>> +	if (error) {
>> +		log("Error in ECC-based read: %d", error);
>> +		goto exit_nfc;
>> +	}
>> +
>> +	/* handle the block mark swapping */
>> +	mil_handle_block_mark_swapping(this, payload_virt, auxiliary_virt);
>> +
>> +	/* Loop over status bytes, accumulating ECC status. */
>> +	failed		= 0;
>> +	corrected	= 0;
>> +	status		= ((unsigned char *) auxiliary_virt) +
>> +					nfc_geo->auxiliary_status_offset;
>>
> Useless cast.
>> +
>> +	for (i = 0; i<  nfc_geo->ecc_chunk_count; i++, status++) {
>> +		if ((*status == STATUS_GOOD) || (*status == STATUS_ERASED))
>> +			continue;
>> +
>> +		if (*status == STATUS_UNCORRECTABLE) {
>> +			failed++;
>> +			continue;
>> +		}
>> +		corrected += *status;
>> +	}
>> +
>> +	/*
>> +	 * Propagate ECC status to the owning MTD only when failed or
>> +	 * corrected times nearly reaches our ECC correction threshold.
>> +	 */
>> +	if (failed || corrected>= (nfc_geo->ecc_strength - 1)) {
>> +		mtd->ecc_stats.failed    += failed;
>> +		mtd->ecc_stats.corrected += corrected;
>> +	}
>> +
>> +	/*
>> +	 * It's time to deliver the OOB bytes. See mil_ecc_read_oob() for
>> +	 * details about our policy for delivering the OOB.
>> +	 *
>> +	 * We fill the caller's buffer with set bits, and then copy the block
>> +	 * mark to th caller's buffer. Note that, if block mark swapping was
>> +	 * necessary, it has already been done, so we can rely on the first
>> +	 * byte of the auxiliary buffer to contain the block mark.
>> +	 */
>> +	memset(nand->oob_poi, ~0, mtd->oobsize);
>> +	nand->oob_poi[0] = ((uint8_t *) auxiliary_virt)[0];
>> +
>> +exit_nfc:
>> +	read_page_end(this, buf, mtd->writesize,
>> +					mil->payload_virt, mil->payload_phys,
>> +					nfc_geo->payload_size_in_bytes,
>> +					payload_virt, payload_phys);
>> +	return error;
>> +}
>> +
>> +static void mil_ecc_write_page(struct mtd_info *mtd,
>> +				struct nand_chip *nand, const uint8_t *buf)
>> +{
>> +	struct gpmi_nfc_data    *this    = nand->priv;
>> +	struct nfc_hal          *nfc     =  this->nfc;
>> +	struct nfc_geometry     *nfc_geo =&this->nfc_geometry;
>> +	struct boot_rom_helper  *rom     =  this->rom;
>> +	struct mil              *mil     =&this->mil;
>> +	const void              *payload_virt   =  0;
>> +	dma_addr_t              payload_phys    = ~0;
>> +	const void              *auxiliary_virt =  0;
>> +	dma_addr_t              auxiliary_phys  = ~0;
>>
> Useless initialization.
>
>> +	int                     error;
>> +
>> +	if (rom->swap_block_mark) {
>> +		/*
>> +		 * If control arrives here, we're doing block mark swapping.
>> +		 * Since we can't modify the caller's buffers, we must copy them
>> +		 * into our own.
>> +		 */
>> +		memcpy(mil->payload_virt, buf, mtd->writesize);
>> +		payload_virt = mil->payload_virt;
>> +		payload_phys = mil->payload_phys;
>> +
>> +		memcpy(mil->auxiliary_virt, nand->oob_poi,
>> +				nfc_geo->auxiliary_size_in_bytes);
>> +		auxiliary_virt = mil->auxiliary_virt;
>> +		auxiliary_phys = mil->auxiliary_phys;
>> +
>> +		/* Handle block mark swapping. */
>> +		mil_handle_block_mark_swapping(this,
>> +				(void *) payload_virt, (void *) auxiliary_virt);
>> +	} else {
>> +		/*
>> +		 * If control arrives here, we're not doing block mark swapping,
>> +		 * so we can to try and use the caller's buffers.
>> +		 */
>> +		error = send_page_prepare(this,
>> +				buf, mtd->writesize,
>> +				mil->payload_virt, mil->payload_phys,
>> +				nfc_geo->payload_size_in_bytes,
>> +				&payload_virt,&payload_phys);
>> +		if (error) {
>> +			log("Inadequate payload DMA buffer");
>> +			return;
>> +		}
>> +
>> +		error = send_page_prepare(this,
>> +				nand->oob_poi, mtd->oobsize,
>> +				mil->auxiliary_virt, mil->auxiliary_phys,
>> +				nfc_geo->auxiliary_size_in_bytes,
>> +				&auxiliary_virt,&auxiliary_phys);
>> +		if (error) {
>> +			log("Inadequate auxiliary DMA buffer");
>> +			goto exit_auxiliary;
>> +		}
>> +	}
>> +
>> +	/* Ask the NFC. */
>> +	error = nfc->send_page(this, payload_phys, auxiliary_phys);
>> +	if (error)
>> +		log("Error in ECC-based write: %d", error);
>> +
>> +	if (!rom->swap_block_mark) {
>> +		send_page_end(this, nand->oob_poi, mtd->oobsize,
>> +				mil->auxiliary_virt, mil->auxiliary_phys,
>> +				nfc_geo->auxiliary_size_in_bytes,
>> +				auxiliary_virt, auxiliary_phys);
>> +exit_auxiliary:
>> +		send_page_end(this, buf, mtd->writesize,
>> +				mil->payload_virt, mil->payload_phys,
>> +				nfc_geo->payload_size_in_bytes,
>> +				payload_virt, payload_phys);
>> +	}
>> +}
>> +
>> +/**
>> + * mil_hook_block_markbad() - Hooked MTD Interface block_markbad().
>> + *
>> + * This function is a veneer that replaces the function originally installed by
>> + * the NAND Flash MTD code. See the description of the marking_a_bad_block field
>> + * in struct mil for more information about this.
>> + *
>> + * @mtd:  A pointer to the MTD.
>> + * @ofs:  Byte address of the block to mark.
>> + */
>> +static int mil_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
>> +{
>> +	register struct nand_chip  *chip = mtd->priv;
>> +	struct gpmi_nfc_data       *this = chip->priv;
>> +	struct mil                 *mil  =&this->mil;
>> +	int                        ret;
>> +
>> +	mil->marking_a_bad_block = true;
>> +	ret = mil->hooked_block_markbad(mtd, ofs);
>> +	mil->marking_a_bad_block = false;
>> +	return ret;
>> +}
>> +
>> +/**
>> + * mil_ecc_read_oob() - MTD Interface ecc.read_oob().
>> + *
>> + * There are several places in this driver where we have to handle the OOB and
>> + * block marks. This is the function where things are the most complicated, so
>> + * this is where we try to explain it all. All the other places refer back to
>> + * here.
>> + *
>> + * These are the rules, in order of decreasing importance:
>> + *
>> + * 1) Nothing the caller does can be allowed to imperil the block mark, so all
>> + *    write operations take measures to protect it.
>> + *
>> + * 2) In read operations, the first byte of the OOB we return must reflect the
>> + *    true state of the block mark, no matter where that block mark appears in
>> + *    the physical page.
>> + *
>> + * 3) ECC-based read operations return an OOB full of set bits (since we never
>> + *    allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
>> + *    return).
>> + *
>> + * 4) "Raw" read operations return a direct view of the physical bytes in the
>> + *    page, using the conventional definition of which bytes are data and which
>> + *    are OOB. This gives the caller a way to see the actual, physical bytes
>> + *    in the page, without the distortions applied by our ECC engine.
>> + *
>> + *
>> + * What we do for this specific read operation depends on two questions:
>> + *
>> + * 1) Are we doing a "raw" read, or an ECC-based read?
>> + *
>> + * 2) Are we using block mark swapping or transcription?
>> + *
>> + * There are four cases, illustrated by the following Karnaugh map:
>> + *
>> + *                    |           Raw           |         ECC-based       |
>> + *       -------------+-------------------------+-------------------------+
>> + *                    | Read the conventional   |                         |
>> + *                    | OOB at the end of the   |                         |
>> + *       Swapping     | page and return it. It  |                         |
>> + *                    | contains exactly what   |                         |
>> + *                    | we want.                | Read the block mark and |
>> + *       -------------+-------------------------+ return it in a buffer   |
>> + *                    | Read the conventional   | full of set bits.       |
>> + *                    | OOB at the end of the   |                         |
>> + *                    | page and also the block |                         |
>> + *       Transcribing | mark in the metadata.   |                         |
>> + *                    | Copy the block mark     |                         |
>> + *                    | into the first byte of  |                         |
>> + *                    | the OOB.                |                         |
>> + *       -------------+-------------------------+-------------------------+
>> + *
>> + * Note that we break rule #4 in the Transcribing/Raw case because we're not
>> + * giving an accurate view of the actual, physical bytes in the page (we're
>> + * overwriting the block mark). That's OK because it's more important to follow
>> + * rule #2.
>> + *
>> + * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
>> + * easy. When reading a page, for example, the NAND Flash MTD code calls our
>> + * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
>> + * ECC-based or raw view of the page is implicit in which function it calls
>> + * (there is a similar pair of ECC-based/raw functions for writing).
>> + *
>> + * Since MTD assumes the OOB is not covered by ECC, there is no pair of
>> + * ECC-based/raw functions for reading or or writing the OOB. The fact that the
>> + * caller wants an ECC-based or raw view of the page is not propagated down to
>> + * this driver.
>> + *
>> + * @mtd:     A pointer to the owning MTD.
>> + * @nand:    A pointer to the owning NAND Flash MTD.
>> + * @page:    The page number to read.
>> + * @sndcmd:  Indicates this function should send a command to the chip before
>> + *           reading the out-of-band bytes. This is only false for small page
>> + *           chips that support auto-increment.
>> + */
>> +static int mil_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
>> +							int page, int sndcmd)
>> +{
>> +	struct gpmi_nfc_data      *this     = nand->priv;
>> +	struct boot_rom_helper    *rom      =  this->rom;
>> +
>> +	/* clear the OOB buffer */
>> +	memset(nand->oob_poi, ~0, mtd->oobsize);
>> +
>> +	/* Read out the conventional OOB. */
>> +	nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
>> +	nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
>> +
>> +	/*
>> +	 * Now, we want to make sure the block mark is correct. In the
>> +	 * Swapping/Raw case, we already have it. Otherwise, we need to
>> +	 * explicitly read it.
>> +	 */
>> +	if (!rom->swap_block_mark) {
>> +		/* Read the block mark into the first byte of the OOB buffer. */
>> +		nand->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
>> +		nand->oob_poi[0] = nand->read_byte(mtd);
>> +	}
>> +
>> +	/*
>> +	 * Return true, indicating that the next call to this function must send
>> +	 * a command.
>> +	 */
>> +	return true;
>> +}
>> +
>> +static int mil_ecc_write_oob(struct mtd_info *mtd,
>> +					struct nand_chip *nand, int page)
>> +{
>> +	struct gpmi_nfc_data      *this     = nand->priv;
>> +	struct device             *dev      =  this->dev;
>> +	struct mil                *mil      =&this->mil;
>> +	struct boot_rom_helper    *rom      =  this->rom;
>> +	uint8_t                   block_mark = 0;
>> +	int                       block_mark_column;
>> +	int                       status;
>> +	int                       error = 0;
>> +
>> +	/*
>> +	 * There are fundamental incompatibilities between the i.MX GPMI NFC and
>> +	 * the NAND Flash MTD model that make it essentially impossible to write
>> +	 * the out-of-band bytes.
>> +	 *
>> +	 * We permit *ONE* exception. If the *intent* of writing the OOB is to
>> +	 * mark a block bad, we can do that.
>> +	 */
>> +	if (!mil->marking_a_bad_block) {
>> +		dev_emerg(dev, "This driver doesn't support writing the OOB\n");
>> +		WARN_ON(1);
>> +		error = -EIO;
>> +		goto exit;
>> +	}
>> +
>> +	/*
>> +	 * If control arrives here, we're marking a block bad. First, figure out
>> +	 * where the block mark is.
>> +	 *
>> +	 * If we're using swapping, the block mark is in the conventional
>> +	 * location. Otherwise, we're using transcription, and the block mark
>> +	 * appears in the first byte of the page.
>> +	 */
>> +	if (rom->swap_block_mark)
>> +		block_mark_column = mtd->writesize;
>> +	else
>> +		block_mark_column = 0;
>> +
>> +	/* Write the block mark. */
>> +	nand->cmdfunc(mtd, NAND_CMD_SEQIN, block_mark_column, page);
>> +	nand->write_buf(mtd,&block_mark, 1);
>>
> DMA mapping memory from stack again.
thanks.
>> +	nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
>> +
>> +	status = nand->waitfunc(mtd, nand);
>> +
>> +	/* Check if it worked. */
>> +	if (status&  NAND_STATUS_FAIL)
>> +		error = -EIO;
>> +exit:
>> +	return error;
>> +}
>> +
>> +/**
>> + * mil_block_bad - Claims all blocks are good.
>> + *
>> + * In principle, this function is *only* called when the NAND Flash MTD system
>> + * isn't allowed to keep an in-memory bad block table, so it is forced to ask
>> + * the driver for bad block information.
>> + *
>> + * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
>> + * this function is *only* called when we take it away.
>> + *
>> + * We take away the in-memory BBT when the user sets the "ignorebad" parameter,
>> + * which indicates that all blocks should be reported good.
>> + *
>> + * Thus, this function is only called when we want *all* blocks to look good,
>> + * so it *always* return success.
>> + *
>> + * @mtd:      Ignored.
>> + * @ofs:      Ignored.
>> + * @getchip:  Ignored.
>> + */
>> +static int mil_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
>> +{
>> +	return 0;
>> +}
>> +
>> +/* Set up the Boot ROM Helper geometry. */
>> +static int mil_set_boot_rom_helper_geometry(struct gpmi_nfc_data  *this)
>> +{
>> +	struct boot_rom_helper    *rom =  this->rom;
>> +	struct boot_rom_geometry  *geo =&this->rom_geometry;
>> +
>> +	if (rom->set_geometry(this))
>> +		return !0;
>> +
>> +	pr_info("--------------------------------------------\n");
>> +	pr_info("	Boot ROM Geometry\n");
>> +	pr_info("--------------------------------------------\n");
>> +	pr_info("Boot Area Count            : %u\n", geo->boot_area_count);
>> +	pr_info("Boot Area Size in Bytes    : %u (0x%x)\n",
>> +					geo->boot_area_size_in_bytes,
>> +					geo->boot_area_size_in_bytes);
>> +	pr_info("Stride Size in Pages       : %u\n", geo->stride_size_in_pages);
>> +	pr_info("Search Area Stride Exponent: %u\n",
>> +					geo->search_area_stride_exponent);
>> +	return 0;
>> +}
>> +
>> +static int mil_set_geometry(struct gpmi_nfc_data *this)
>> +{
>> +	struct nfc_hal *nfc = this->nfc;
>> +	struct nfc_geometry *geo =&this->nfc_geometry;
>> +
>> +	/* Free the temporary DMA memory for read ID case */
>> +	mil_free_dma_buffer(this);
>> +
>> +	/* Set up the NFC geometry which is used by BCH. */
>> +	if (nfc->set_geometry(this))
>> +		return -ENXIO;
>>
> Promote the error code returned by set_geometry().
>
ok. thanks.
>> +	pr_info("---------------------------------------\n");
>> +	pr_info("	NFC Geometry (used by BCH)\n");
>> +	pr_info("---------------------------------------\n");
>> +	pr_info("ECC Algorithm          : %s\n", geo->ecc_algorithm);
>> +	pr_info("ECC Strength           : %u\n", geo->ecc_strength);
>> +	pr_info("Page Size in Bytes     : %u\n", geo->page_size_in_bytes);
>> +	pr_info("Metadata Size in Bytes : %u\n", geo->metadata_size_in_bytes);
>> +	pr_info("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size_in_bytes);
>> +	pr_info("ECC Chunk Count        : %u\n", geo->ecc_chunk_count);
>> +	pr_info("Payload Size in Bytes  : %u\n", geo->payload_size_in_bytes);
>> +	pr_info("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size_in_bytes);
>> +	pr_info("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
>> +	pr_info("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
>> +	pr_info("Block Mark Bit Offset  : %u\n", geo->block_mark_bit_offset);
>> +
>> +	/* Alloc the new DMA buffers according to the pagesize and oobsize */
>> +	return mil_alloc_dma_buffer(this);
>> +}
>> +
>> +static int mil_pre_bbt_scan(struct gpmi_nfc_data  *this)
>> +{
>> +	struct boot_rom_helper	*rom	= this->rom;
>> +	int			error	= 0;
>> +
>> +	if (mil_set_boot_rom_helper_geometry(this))
>> +		return -ENXIO;
>>
> Promote the error code returned by mil_set_boot_rom_helper_geometry().
ok.


Huang Shijie

[PATCH 0/7] add the GPMI controller driver for IMX23/IMX28

[Huang Shijie]

The general-purpose media interface(GPMI) controller is a flexible interface
to up to several NAND flashs.

The Bose Ray-Choudhury Hocquenghem(BCH) module is a hardware ECC accelerator.

With the help of BCH, the GPMI controller can choose to do the hardware ECC or
not.

This driver is based the Shawn Guo's DMA patches for IMX23/IMX28,
please refer to :
	http://git.infradead.org/users/vkoul/slave-dma.git/commit/a580b8c5429a624d120cd603e1498bf676e2b4da

add the mtd maillist.	

Huang Shijie (7):
  ARM: add GPMI support for imx23/imx28
  add the common code for GPMI driver
  add the database for the NANDs
  add GPMI support for imx23
  add GPMI support for imx28
  dmaengine: change the flags of request_irq()
  MTD : add GPMI driver in the config and Makefile

 arch/arm/mach-mxs/Kconfig                       |    2 +
 arch/arm/mach-mxs/clock-mx23.c                  |    3 +
 arch/arm/mach-mxs/clock-mx28.c                  |    3 +
 arch/arm/mach-mxs/devices-mx23.h                |    3 +
 arch/arm/mach-mxs/devices-mx28.h                |    3 +
 arch/arm/mach-mxs/devices/Kconfig               |    3 +
 arch/arm/mach-mxs/devices/Makefile              |    1 +
 arch/arm/mach-mxs/devices/platform-gpmi.c       |  144 +++
 arch/arm/mach-mxs/include/mach/devices-common.h |    4 +
 arch/arm/mach-mxs/include/mach/gpmi-nfc.h       |   75 ++
 arch/arm/mach-mxs/mach-mx23evk.c                |   37 +
 arch/arm/mach-mxs/mach-mx28evk.c                |   37 +
 drivers/dma/mxs-dma.c                           |    2 +-
 drivers/mtd/nand/Kconfig                        |   10 +
 drivers/mtd/nand/Makefile                       |    1 +
 drivers/mtd/nand/gpmi-nfc/Makefile              |   10 +
 drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h      |  550 +++++++++++
 drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h      |  557 ++++++++++++
 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c       |  524 +++++++++++
 drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h            |  520 +++++++++++
 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h     |  416 +++++++++
 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h     |  421 +++++++++
 drivers/mtd/nand/gpmi-nfc/hal-common.c          |  816 +++++++++++++++++
 drivers/mtd/nand/gpmi-nfc/hal-imx23.c           |  556 ++++++++++++
 drivers/mtd/nand/gpmi-nfc/hal-imx28.c           |  503 +++++++++++
 drivers/mtd/nand/gpmi-nfc/mil.c                 | 1104 +++++++++++++++++++++++
 drivers/mtd/nand/gpmi-nfc/nand_device_info.c    |  181 ++++
 drivers/mtd/nand/gpmi-nfc/nand_device_info.h    |  145 +++
 drivers/mtd/nand/gpmi-nfc/rom-common.c          |   48 +
 drivers/mtd/nand/gpmi-nfc/rom-imx23.c           |  300 ++++++
 drivers/mtd/nand/gpmi-nfc/rom-imx28.c           |   66 ++
 31 files changed, 7044 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-mxs/devices/platform-gpmi.c
 create mode 100644 arch/arm/mach-mxs/include/mach/gpmi-nfc.h
 create mode 100644 drivers/mtd/nand/gpmi-nfc/Makefile
 create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
 create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
 create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
 create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
 create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
 create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
 create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-common.c
 create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx23.c
 create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx28.c
 create mode 100644 drivers/mtd/nand/gpmi-nfc/mil.c
 create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.c
 create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.h
 create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-common.c
 create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx23.c
 create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx28.c

[PATCH 5/7] add GPMI support for imx28

[Huang Shijie]

These files contain the code to implement the GPMI in the imx28.

Signed-off-by: Huang Shijie <b32955@freescale.com>
---
 drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h  |  557 +++++++++++++++++++++++++++
 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h |  421 ++++++++++++++++++++
 drivers/mtd/nand/gpmi-nfc/hal-imx28.c       |  503 ++++++++++++++++++++++++
 drivers/mtd/nand/gpmi-nfc/rom-imx28.c       |   66 ++++
 4 files changed, 1547 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
 create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
 create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx28.c
 create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx28.c

diff --git a/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
new file mode 100644
index 0000000..692db08
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
@@ -0,0 +1,557 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * Xml Revision: 2.5
+ * Template revision: 26195
+ */
+
+#ifndef __GPMI_NFC_BCH_REGS_H
+#define __GPMI_NFC_BCH_REGS_H
+
+/*============================================================================*/
+
+#define HW_BCH_CTRL	(0x00000000)
+#define HW_BCH_CTRL_SET	(0x00000004)
+#define HW_BCH_CTRL_CLR	(0x00000008)
+#define HW_BCH_CTRL_TOG	(0x0000000c)
+
+#define BM_BCH_CTRL_SFTRST	0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN   0x0
+#define BV_BCH_CTRL_SFTRST__RESET 0x1
+#define BM_BCH_CTRL_CLKGATE	0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN     0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
+#define BP_BCH_CTRL_RSVD5	23
+#define BM_BCH_CTRL_RSVD5	0x3F800000
+#define BF_BCH_CTRL_RSVD5(v)  \
+		(((v) << 23) & BM_BCH_CTRL_RSVD5)
+#define BM_BCH_CTRL_DEBUGSYNDROME	0x00400000
+#define BP_BCH_CTRL_RSVD4	20
+#define BM_BCH_CTRL_RSVD4	0x00300000
+#define BF_BCH_CTRL_RSVD4(v)  \
+		(((v) << 20) & BM_BCH_CTRL_RSVD4)
+#define BP_BCH_CTRL_M2M_LAYOUT	18
+#define BM_BCH_CTRL_M2M_LAYOUT	0x000C0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v)  \
+		(((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT)
+#define BM_BCH_CTRL_M2M_ENCODE	0x00020000
+#define BM_BCH_CTRL_M2M_ENABLE	0x00010000
+#define BP_BCH_CTRL_RSVD3	11
+#define BM_BCH_CTRL_RSVD3	0x0000F800
+#define BF_BCH_CTRL_RSVD3(v)  \
+		(((v) << 11) & BM_BCH_CTRL_RSVD3)
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN	0x00000400
+#define BM_BCH_CTRL_RSVD2	0x00000200
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN	0x00000100
+#define BP_BCH_CTRL_RSVD1	4
+#define BM_BCH_CTRL_RSVD1	0x000000F0
+#define BF_BCH_CTRL_RSVD1(v)  \
+		(((v) << 4) & BM_BCH_CTRL_RSVD1)
+#define BM_BCH_CTRL_BM_ERROR_IRQ	0x00000008
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ	0x00000004
+#define BM_BCH_CTRL_RSVD0	0x00000002
+#define BM_BCH_CTRL_COMPLETE_IRQ	0x00000001
+
+/*============================================================================*/
+
+#define HW_BCH_STATUS0	(0x00000010)
+
+#define BP_BCH_STATUS0_HANDLE	20
+#define BM_BCH_STATUS0_HANDLE	0xFFF00000
+#define BF_BCH_STATUS0_HANDLE(v) \
+		(((v) << 20) & BM_BCH_STATUS0_HANDLE)
+#define BP_BCH_STATUS0_COMPLETED_CE	16
+#define BM_BCH_STATUS0_COMPLETED_CE	0x000F0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v)  \
+		(((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE)
+#define BP_BCH_STATUS0_STATUS_BLK0	8
+#define BM_BCH_STATUS0_STATUS_BLK0	0x0000FF00
+#define BF_BCH_STATUS0_STATUS_BLK0(v)  \
+		(((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0)
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO          0x00
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1        0x01
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2        0x02
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3        0x03
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4        0x04
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED        0xFF
+#define BP_BCH_STATUS0_RSVD1	5
+#define BM_BCH_STATUS0_RSVD1	0x000000E0
+#define BF_BCH_STATUS0_RSVD1(v)  \
+		(((v) << 5) & BM_BCH_STATUS0_RSVD1)
+#define BM_BCH_STATUS0_ALLONES	0x00000010
+#define BM_BCH_STATUS0_CORRECTED	0x00000008
+#define BM_BCH_STATUS0_UNCORRECTABLE	0x00000004
+#define BP_BCH_STATUS0_RSVD0	0
+#define BM_BCH_STATUS0_RSVD0	0x00000003
+#define BF_BCH_STATUS0_RSVD0(v)  \
+		(((v) << 0) & BM_BCH_STATUS0_RSVD0)
+
+/*============================================================================*/
+
+#define HW_BCH_MODE	(0x00000020)
+
+#define BP_BCH_MODE_RSVD	8
+#define BM_BCH_MODE_RSVD	0xFFFFFF00
+#define BF_BCH_MODE_RSVD(v) \
+		(((v) << 8) & BM_BCH_MODE_RSVD)
+#define BP_BCH_MODE_ERASE_THRESHOLD	0
+#define BM_BCH_MODE_ERASE_THRESHOLD	0x000000FF
+#define BF_BCH_MODE_ERASE_THRESHOLD(v)  \
+		(((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
+
+/*============================================================================*/
+
+#define HW_BCH_ENCODEPTR	(0x00000030)
+
+#define BP_BCH_ENCODEPTR_ADDR	0
+#define BM_BCH_ENCODEPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_ENCODEPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DATAPTR	(0x00000040)
+
+#define BP_BCH_DATAPTR_ADDR	0
+#define BM_BCH_DATAPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_DATAPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_METAPTR	(0x00000050)
+
+#define BP_BCH_METAPTR_ADDR	0
+#define BM_BCH_METAPTR_ADDR	0xFFFFFFFF
+#define BF_BCH_METAPTR_ADDR(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_LAYOUTSELECT	(0x00000070)
+
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT	30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT	0xC0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \
+		(((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT	28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT	0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v)  \
+		(((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT	26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT	0x0C000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v)  \
+		(((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT	24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT	0x03000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v)  \
+		(((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT	22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT	0x00C00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v)  \
+		(((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT	20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT	0x00300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v)  \
+		(((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT	18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT	0x000C0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v)  \
+		(((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT	16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT	0x00030000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v)  \
+		(((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT	14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT	0x0000C000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v)  \
+		(((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT	12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT	0x00003000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v)  \
+		(((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT	10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT	0x00000C00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v)  \
+		(((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT	8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT	0x00000300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v)  \
+		(((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT	6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT	0x000000C0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v)  \
+		(((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT	4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT	0x00000030
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v)  \
+		(((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT	2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT	0x0000000C
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v)  \
+		(((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT	0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT	0x00000003
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v)  \
+		(((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT0	(0x00000080)
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH0LAYOUT0_ECC0	12
+#define BM_BCH_FLASH0LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0)
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT1	(0x00000090)
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH0LAYOUT1_ECCN	12
+#define BM_BCH_FLASH0LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN)
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT0	(0x000000a0)
+
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH1LAYOUT0_ECC0	12
+#define BM_BCH_FLASH1LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0)
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT1	(0x000000b0)
+
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH1LAYOUT1_ECCN	12
+#define BM_BCH_FLASH1LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN)
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT0	(0x000000c0)
+
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH2LAYOUT0_ECC0	12
+#define BM_BCH_FLASH2LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0)
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT1	(0x000000d0)
+
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH2LAYOUT1_ECCN	12
+#define BM_BCH_FLASH2LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN)
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT0	(0x000000e0)
+
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS	24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS	0xFF000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \
+		(((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE	16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE	0x00FF0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v)  \
+		(((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH3LAYOUT0_ECC0	12
+#define BM_BCH_FLASH3LAYOUT0_ECC0	0x0000F000
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v)  \
+		(((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0)
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE	0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE	0x00000FFF
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT1	(0x000000f0)
+
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE	16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE	0xFFFF0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \
+		(((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH3LAYOUT1_ECCN	12
+#define BM_BCH_FLASH3LAYOUT1_ECCN	0x0000F000
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v)  \
+		(((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN)
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE  0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2  0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4  0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6  0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8  0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE	0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE	0x00000FFF
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v)  \
+		(((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_DEBUG0	(0x00000100)
+#define HW_BCH_DEBUG0_SET	(0x00000104)
+#define HW_BCH_DEBUG0_CLR	(0x00000108)
+#define HW_BCH_DEBUG0_TOG	(0x0000010c)
+
+#define BP_BCH_DEBUG0_RSVD1	27
+#define BM_BCH_DEBUG0_RSVD1	0xF8000000
+#define BF_BCH_DEBUG0_RSVD1(v) \
+		(((v) << 27) & BM_BCH_DEBUG0_RSVD1)
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE	0x04000000
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE	0x02000000
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL	16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL	0x01FF0000
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)  \
+		(((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND	0x00008000
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG	0x00004000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX  0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K	0x00002000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK	0x00001000
+#define BM_BCH_DEBUG0_KES_STANDALONE	0x00000800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL    0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP	0x00000400
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL	0x00000200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT   0x1
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS	0x00000100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL    0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
+#define BP_BCH_DEBUG0_RSVD0	6
+#define BM_BCH_DEBUG0_RSVD0	0x000000C0
+#define BF_BCH_DEBUG0_RSVD0(v)  \
+		(((v) << 6) & BM_BCH_DEBUG0_RSVD0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT	0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT	0x0000003F
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v)  \
+		(((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGKESREAD	(0x00000110)
+
+#define BP_BCH_DBGKESREAD_VALUES	0
+#define BM_BCH_DBGKESREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGKESREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGCSFEREAD	(0x00000120)
+
+#define BP_BCH_DBGCSFEREAD_VALUES	0
+#define BM_BCH_DBGCSFEREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGCSFEREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGSYNDGENREAD	(0x00000130)
+
+#define BP_BCH_DBGSYNDGENREAD_VALUES	0
+#define BM_BCH_DBGSYNDGENREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGAHBMREAD	(0x00000140)
+
+#define BP_BCH_DBGAHBMREAD_VALUES	0
+#define BM_BCH_DBGAHBMREAD_VALUES	0xFFFFFFFF
+#define BF_BCH_DBGAHBMREAD_VALUES(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_BLOCKNAME	(0x00000150)
+
+#define BP_BCH_BLOCKNAME_NAME	0
+#define BM_BCH_BLOCKNAME_NAME	0xFFFFFFFF
+#define BF_BCH_BLOCKNAME_NAME(v)	(v)
+
+/*============================================================================*/
+
+#define HW_BCH_VERSION	(0x00000160)
+
+#define BP_BCH_VERSION_MAJOR	24
+#define BM_BCH_VERSION_MAJOR	0xFF000000
+#define BF_BCH_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_BCH_VERSION_MAJOR)
+#define BP_BCH_VERSION_MINOR	16
+#define BM_BCH_VERSION_MINOR	0x00FF0000
+#define BF_BCH_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_BCH_VERSION_MINOR)
+#define BP_BCH_VERSION_STEP	0
+#define BM_BCH_VERSION_STEP	0x0000FFFF
+#define BF_BCH_VERSION_STEP(v)  \
+		(((v) << 0) & BM_BCH_VERSION_STEP)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
new file mode 100644
index 0000000..dcb3b7d
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
@@ -0,0 +1,421 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * Xml Revision: 2.2
+ * Template revision: 26195
+ */
+
+#ifndef __GPMI_NFC_GPMI_REGS_H
+#define __GPMI_NFC_GPMI_REGS_H
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL0	(0x00000000)
+#define HW_GPMI_CTRL0_SET	(0x00000004)
+#define HW_GPMI_CTRL0_CLR	(0x00000008)
+#define HW_GPMI_CTRL0_TOG	(0x0000000c)
+
+#define BM_GPMI_CTRL0_SFTRST	0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN   0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
+#define BM_GPMI_CTRL0_CLKGATE	0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN     0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
+#define BM_GPMI_CTRL0_RUN	0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE 0x0
+#define BV_GPMI_CTRL0_RUN__BUSY 0x1
+#define BM_GPMI_CTRL0_DEV_IRQ_EN	0x10000000
+#define BM_GPMI_CTRL0_LOCK_CS	0x08000000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED  0x1
+#define BM_GPMI_CTRL0_UDMA	0x04000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED  0x1
+#define BP_GPMI_CTRL0_COMMAND_MODE	24
+#define BM_GPMI_CTRL0_COMMAND_MODE	0x03000000
+#define BF_GPMI_CTRL0_COMMAND_MODE(v)  \
+		(((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE            0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ             0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY   0x3
+#define BM_GPMI_CTRL0_WORD_LENGTH	0x00800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT  0x1
+#define BP_GPMI_CTRL0_CS	20
+#define BM_GPMI_CTRL0_CS	0x00700000
+#define BF_GPMI_CTRL0_CS(v)  \
+		(((v) << 20) & BM_GPMI_CTRL0_CS)
+#define BP_GPMI_CTRL0_ADDRESS	17
+#define BM_GPMI_CTRL0_ADDRESS	0x000E0000
+#define BF_GPMI_CTRL0_ADDRESS(v)  \
+		(((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE  0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE  0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT	0x00010000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED  0x1
+#define BP_GPMI_CTRL0_XFER_COUNT	0
+#define BM_GPMI_CTRL0_XFER_COUNT	0x0000FFFF
+#define BF_GPMI_CTRL0_XFER_COUNT(v)  \
+		(((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_COMPARE	(0x00000010)
+
+#define BP_GPMI_COMPARE_MASK	16
+#define BM_GPMI_COMPARE_MASK	0xFFFF0000
+#define BF_GPMI_COMPARE_MASK(v) \
+		(((v) << 16) & BM_GPMI_COMPARE_MASK)
+#define BP_GPMI_COMPARE_REFERENCE	0
+#define BM_GPMI_COMPARE_REFERENCE	0x0000FFFF
+#define BF_GPMI_COMPARE_REFERENCE(v)  \
+		(((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCTRL	(0x00000020)
+#define HW_GPMI_ECCCTRL_SET	(0x00000024)
+#define HW_GPMI_ECCCTRL_CLR	(0x00000028)
+#define HW_GPMI_ECCCTRL_TOG	(0x0000002c)
+
+#define BP_GPMI_ECCCTRL_HANDLE	16
+#define BM_GPMI_ECCCTRL_HANDLE	0xFFFF0000
+#define BF_GPMI_ECCCTRL_HANDLE(v) \
+		(((v) << 16) & BM_GPMI_ECCCTRL_HANDLE)
+#define BM_GPMI_ECCCTRL_RSVD2	0x00008000
+#define BP_GPMI_ECCCTRL_ECC_CMD	13
+#define BM_GPMI_ECCCTRL_ECC_CMD	0x00006000
+#define BF_GPMI_ECCCTRL_ECC_CMD(v)  \
+		(((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE   0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE   0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3
+#define BM_GPMI_ECCCTRL_ENABLE_ECC	0x00001000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE  0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
+#define BP_GPMI_ECCCTRL_RSVD1	9
+#define BM_GPMI_ECCCTRL_RSVD1	0x00000E00
+#define BF_GPMI_ECCCTRL_RSVD1(v)  \
+		(((v) << 9) & BM_GPMI_ECCCTRL_RSVD1)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK	0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK	0x000001FF
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)  \
+		(((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE    0x1FF
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCOUNT	(0x00000030)
+
+#define BP_GPMI_ECCCOUNT_RSVD2	16
+#define BM_GPMI_ECCCOUNT_RSVD2	0xFFFF0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v) \
+		(((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2)
+#define BP_GPMI_ECCCOUNT_COUNT	0
+#define BM_GPMI_ECCCOUNT_COUNT	0x0000FFFF
+#define BF_GPMI_ECCCOUNT_COUNT(v)  \
+		(((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_PAYLOAD	(0x00000040)
+
+#define BP_GPMI_PAYLOAD_ADDRESS	2
+#define BM_GPMI_PAYLOAD_ADDRESS	0xFFFFFFFC
+#define BF_GPMI_PAYLOAD_ADDRESS(v) \
+		(((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
+#define BP_GPMI_PAYLOAD_RSVD0	0
+#define BM_GPMI_PAYLOAD_RSVD0	0x00000003
+#define BF_GPMI_PAYLOAD_RSVD0(v)  \
+		(((v) << 0) & BM_GPMI_PAYLOAD_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_AUXILIARY	(0x00000050)
+
+#define BP_GPMI_AUXILIARY_ADDRESS	2
+#define BM_GPMI_AUXILIARY_ADDRESS	0xFFFFFFFC
+#define BF_GPMI_AUXILIARY_ADDRESS(v) \
+		(((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
+#define BP_GPMI_AUXILIARY_RSVD0	0
+#define BM_GPMI_AUXILIARY_RSVD0	0x00000003
+#define BF_GPMI_AUXILIARY_RSVD0(v)  \
+		(((v) << 0) & BM_GPMI_AUXILIARY_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL1	(0x00000060)
+#define HW_GPMI_CTRL1_SET	(0x00000064)
+#define HW_GPMI_CTRL1_CLR	(0x00000068)
+#define HW_GPMI_CTRL1_TOG	(0x0000006c)
+
+#define BP_GPMI_CTRL1_RSVD2	25
+#define BM_GPMI_CTRL1_RSVD2	0xFE000000
+#define BF_GPMI_CTRL1_RSVD2(v) \
+		(((v) << 25) & BM_GPMI_CTRL1_RSVD2)
+#define BM_GPMI_CTRL1_DECOUPLE_CS	0x01000000
+#define BP_GPMI_CTRL1_WRN_DLY_SEL	22
+#define BM_GPMI_CTRL1_WRN_DLY_SEL	0x00C00000
+#define BF_GPMI_CTRL1_WRN_DLY_SEL(v)  \
+		(((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL)
+#define BM_GPMI_CTRL1_RSVD1	0x00200000
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN	0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY	0x00080000
+#define BM_GPMI_CTRL1_BCH_MODE	0x00040000
+#define BP_GPMI_CTRL1_DLL_ENABLE	17
+#define BM_GPMI_CTRL1_DLL_ENABLE	0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD	16
+#define BM_GPMI_CTRL1_HALF_PERIOD	0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY	12
+#define BM_GPMI_CTRL1_RDN_DELAY	0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v)  \
+		(((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE	0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ	0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ	0x00000200
+#define BM_GPMI_CTRL1_BURST_EN	0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST	0x00000080
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL	4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL	0x00000070
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v)  \
+		(((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL)
+#define BM_GPMI_CTRL1_DEV_RESET	0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED  0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY	0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW  0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE	0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE	0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA  0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING0	(0x00000070)
+
+#define BP_GPMI_TIMING0_RSVD1	24
+#define BM_GPMI_TIMING0_RSVD1	0xFF000000
+#define BF_GPMI_TIMING0_RSVD1(v) \
+		(((v) << 24) & BM_GPMI_TIMING0_RSVD1)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP	16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP	0x00FF0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)  \
+		(((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+#define BP_GPMI_TIMING0_DATA_HOLD	8
+#define BM_GPMI_TIMING0_DATA_HOLD	0x0000FF00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)  \
+		(((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
+#define BP_GPMI_TIMING0_DATA_SETUP	0
+#define BM_GPMI_TIMING0_DATA_SETUP	0x000000FF
+#define BF_GPMI_TIMING0_DATA_SETUP(v)  \
+		(((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING1	(0x00000080)
+
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT	16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT	0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+		(((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
+#define BP_GPMI_TIMING1_RSVD1	0
+#define BM_GPMI_TIMING1_RSVD1	0x0000FFFF
+#define BF_GPMI_TIMING1_RSVD1(v)  \
+		(((v) << 0) & BM_GPMI_TIMING1_RSVD1)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING2	(0x00000090)
+
+#define BP_GPMI_TIMING2_UDMA_TRP	24
+#define BM_GPMI_TIMING2_UDMA_TRP	0xFF000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v) \
+		(((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP)
+#define BP_GPMI_TIMING2_UDMA_ENV	16
+#define BM_GPMI_TIMING2_UDMA_ENV	0x00FF0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)  \
+		(((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV)
+#define BP_GPMI_TIMING2_UDMA_HOLD	8
+#define BM_GPMI_TIMING2_UDMA_HOLD	0x0000FF00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)  \
+		(((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD)
+#define BP_GPMI_TIMING2_UDMA_SETUP	0
+#define BM_GPMI_TIMING2_UDMA_SETUP	0x000000FF
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)  \
+		(((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DATA	(0x000000a0)
+
+#define BP_GPMI_DATA_DATA	0
+#define BM_GPMI_DATA_DATA	0xFFFFFFFF
+#define BF_GPMI_DATA_DATA(v)	(v)
+
+#define HW_GPMI_STAT	(0x000000b0)
+
+#define BP_GPMI_STAT_READY_BUSY	24
+#define BM_GPMI_STAT_READY_BUSY	0xFF000000
+#define BF_GPMI_STAT_READY_BUSY(v) \
+		(((v) << 24) & BM_GPMI_STAT_READY_BUSY)
+#define BP_GPMI_STAT_RDY_TIMEOUT	16
+#define BM_GPMI_STAT_RDY_TIMEOUT	0x00FF0000
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)  \
+		(((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT)
+#define BM_GPMI_STAT_DEV7_ERROR	0x00008000
+#define BM_GPMI_STAT_DEV6_ERROR	0x00004000
+#define BM_GPMI_STAT_DEV5_ERROR	0x00002000
+#define BM_GPMI_STAT_DEV4_ERROR	0x00001000
+#define BM_GPMI_STAT_DEV3_ERROR	0x00000800
+#define BM_GPMI_STAT_DEV2_ERROR	0x00000400
+#define BM_GPMI_STAT_DEERROR	0x00000200
+#define BM_GPMI_STAT_DEV0_ERROR	0x00000100
+#define BP_GPMI_STAT_RSVD1	5
+#define BM_GPMI_STAT_RSVD1	0x000000E0
+#define BF_GPMI_STAT_RSVD1(v)  \
+		(((v) << 5) & BM_GPMI_STAT_RSVD1)
+#define BM_GPMI_STAT_ATA_IRQ	0x00000010
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK	0x00000008
+#define BM_GPMI_STAT_FIFO_EMPTY	0x00000004
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY     0x1
+#define BM_GPMI_STAT_FIFO_FULL	0x00000002
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL     0x1
+#define BM_GPMI_STAT_PRESENT	0x00000001
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE   0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG	(0x000000c0)
+
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END	24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END	0xFF000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \
+		(((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END)
+#define BP_GPMI_DEBUG_DMA_SENSE	16
+#define BM_GPMI_DEBUG_DMA_SENSE	0x00FF0000
+#define BF_GPMI_DEBUG_DMA_SENSE(v)  \
+		(((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE)
+#define BP_GPMI_DEBUG_DMAREQ	8
+#define BM_GPMI_DEBUG_DMAREQ	0x0000FF00
+#define BF_GPMI_DEBUG_DMAREQ(v)  \
+		(((v) << 8) & BM_GPMI_DEBUG_DMAREQ)
+#define BP_GPMI_DEBUG_CMD_END	0
+#define BM_GPMI_DEBUG_CMD_END	0x000000FF
+#define BF_GPMI_DEBUG_CMD_END(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG_CMD_END)
+
+/*============================================================================*/
+
+#define HW_GPMI_VERSION	(0x000000d0)
+
+#define BP_GPMI_VERSION_MAJOR	24
+#define BM_GPMI_VERSION_MAJOR	0xFF000000
+#define BF_GPMI_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_GPMI_VERSION_MAJOR)
+#define BP_GPMI_VERSION_MINOR	16
+#define BM_GPMI_VERSION_MINOR	0x00FF0000
+#define BF_GPMI_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_GPMI_VERSION_MINOR)
+#define BP_GPMI_VERSION_STEP	0
+#define BM_GPMI_VERSION_STEP	0x0000FFFF
+#define BF_GPMI_VERSION_STEP(v)  \
+		(((v) << 0) & BM_GPMI_VERSION_STEP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG2	(0x000000e0)
+
+#define BP_GPMI_DEBUG2_RSVD1	28
+#define BM_GPMI_DEBUG2_RSVD1	0xF0000000
+#define BF_GPMI_DEBUG2_RSVD1(v) \
+		(((v) << 28) & BM_GPMI_DEBUG2_RSVD1)
+#define BP_GPMI_DEBUG2_UDMA_STATE	24
+#define BM_GPMI_DEBUG2_UDMA_STATE	0x0F000000
+#define BF_GPMI_DEBUG2_UDMA_STATE(v)  \
+		(((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE)
+#define BM_GPMI_DEBUG2_BUSY	0x00800000
+#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0
+#define BV_GPMI_DEBUG2_BUSY__ENABLED  0x1
+#define BP_GPMI_DEBUG2_PIN_STATE	20
+#define BM_GPMI_DEBUG2_PIN_STATE	0x00700000
+#define BF_GPMI_DEBUG2_PIN_STATE(v)  \
+		(((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE)
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE   0x0
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR   0x2
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL  0x3
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD  0x6
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE   0x7
+#define BP_GPMI_DEBUG2_MAIN_STATE	16
+#define BM_GPMI_DEBUG2_MAIN_STATE	0x000F0000
+#define BF_GPMI_DEBUG2_MAIN_STATE(v)  \
+		(((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE)
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE   0x0
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP  0x9
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE   0xA
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE	12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE	0x0000F000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v)  \
+		(((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID	0x00000800
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY	0x00000400
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID	0x00000200
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY	0x00000100
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN	0x00000080
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW	0x00000040
+#define BP_GPMI_DEBUG2_RDN_TAP	0
+#define BM_GPMI_DEBUG2_RDN_TAP	0x0000003F
+#define BF_GPMI_DEBUG2_RDN_TAP(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG3	(0x000000f0)
+
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR	16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR	0xFFFF0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \
+		(((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR	0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR	0x0000FFFF
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v)  \
+		(((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/hal-imx28.c b/drivers/mtd/nand/gpmi-nfc/hal-imx28.c
new file mode 100644
index 0000000..ff87d7f
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/hal-imx28.c
@@ -0,0 +1,503 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+#include "gpmi-regs-imx28.h"
+#include "bch-regs-imx28.h"
+
+static int init_hal_imx28(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+
+	/* Enable the clock. */
+	clk_enable(resources->clock);
+
+	/* Reset the GPMI block. */
+	mxs_reset_block(resources->gpmi_regs);
+
+	/* Choose NAND mode. */
+	__raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+	/* Set the IRQ polarity. */
+	__raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable write protection. */
+	__raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Select BCH ECC. */
+	__raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+				resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* Disable the clock. */
+	clk_disable(resources->clock);
+
+	return 0;
+}
+
+/* Configures the NFC geometry for BCH.  */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+	struct resources     *resources = &this->resources;
+	struct nfc_geometry  *nfc       = &this->nfc_geometry;
+	unsigned int         block_count;
+	unsigned int         block_size;
+	unsigned int         metadata_size;
+	unsigned int         ecc_strength;
+	unsigned int         page_size;
+
+	/* We make the abstract choices in a common function. */
+	if (common_nfc_set_geometry(this))
+		return !0;
+
+	/* Translate the abstract choices into register fields. */
+	block_count   = nfc->ecc_chunk_count - 1;
+	block_size    = nfc->ecc_chunk_size_in_bytes;
+	metadata_size = nfc->metadata_size_in_bytes;
+	ecc_strength  = nfc->ecc_strength >> 1;
+	page_size     = nfc->page_size_in_bytes;
+
+	/* Enable the clock. */
+	clk_enable(resources->clock);
+
+	/*
+	 * Reset the BCH block. Notice that we pass in true for the just_enable
+	 * flag. This is because the soft reset for the version 0 BCH block
+	 * doesn't work and the version 1 BCH block is similar enough that we
+	 * suspect the same (though this has not been officially tested). If you
+	 * try to soft reset a version 0 BCH block, it becomes unusable until
+	 * the next hard reset.
+	 */
+	mxs_reset_block(resources->bch_regs);
+
+	/* Configure layout 0. */
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)     |
+		BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+		BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength)       |
+		BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size)   ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+	__raw_writel(
+		BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)   |
+		BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength)     |
+		BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+		resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+	/* Set *all* chip selects to use layout 0. */
+	__raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+	/* Enable interrupts. */
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+				resources->bch_regs + HW_BCH_CTRL_SET);
+
+	/* Disable the clock. */
+	clk_disable(resources->clock);
+
+	return 0;
+}
+
+static int set_timing(struct gpmi_nfc_data *this,
+			const struct nand_timing *timing)
+{
+	struct nfc_hal  *nfc = this->nfc;
+
+	nfc->timing = *timing;
+	return 0;
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this:                    Per-device data.
+ * @clock_frequency_in_hz:   The clock frequency, in Hz, during the current
+ *                           I/O transaction. If no I/O transaction is in
+ *                           progress, this is the clock frequency during the
+ *                           most recent I/O transaction.
+ * @hardware_timing:         The hardware timing configuration in effect during
+ *                           the current I/O transaction. If no I/O transaction
+ *                           is in progress, this is the hardware timing
+ *                           configuration during the most recent I/O
+ *                           transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+			unsigned long *clock_frequency_in_hz,
+			struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+	struct resources                 *resources = &this->resources;
+	struct nfc_hal                   *nfc       =  this->nfc;
+	unsigned char                    *gpmi_regs = resources->gpmi_regs;
+	uint32_t                         register_image;
+
+	/* Return the clock frequency. */
+	*clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+	/* We'll be reading the hardware, so let's enable the clock. */
+	clk_enable(resources->clock);
+
+	/* Retrieve the hardware timing. */
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+	hardware_timing->data_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+						BP_GPMI_TIMING0_DATA_SETUP;
+
+	hardware_timing->data_hold_in_cycles =
+		(register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+						BP_GPMI_TIMING0_DATA_HOLD;
+
+	hardware_timing->address_setup_in_cycles =
+		(register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+						BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+	register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+	hardware_timing->use_half_periods =
+		(register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+						BP_GPMI_CTRL1_HALF_PERIOD;
+
+	hardware_timing->sample_delay_factor =
+		(register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+						BP_GPMI_CTRL1_RDN_DELAY;
+
+	/* We're done reading the hardware, so disable the clock. */
+	clk_disable(resources->clock);
+}
+
+static void exit(struct gpmi_nfc_data *this)
+{
+}
+
+static void begin(struct gpmi_nfc_data *this)
+{
+	struct resources                 *resources = &this->resources;
+
+	/* Enable the clock. */
+	clk_enable(resources->clock);
+}
+
+static void end(struct gpmi_nfc_data *this)
+{
+	struct resources  *resources = &this->resources;
+	clk_disable(resources->clock);
+}
+
+/* Clears a BCH interrupt. */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+	struct resources  *r = &this->resources;
+
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
+}
+
+/* Returns the Ready/Busy status of the given chip. */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+	struct resources  *resources = &this->resources;
+	uint32_t          mask;
+	uint32_t          register_image;
+
+	/* Extract and return the status. */
+	mask = BF_GPMI_STAT_READY_BUSY(1 << chip);
+	register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT);
+	return !!(register_image & mask);
+}
+
+/* Sends a command and associated addresses. */
+static int send_command(struct gpmi_nfc_data *this)
+{
+	struct dma_chan *channel = get_dma_chan(this);
+	struct mil *mil	= &this->mil;
+	struct dma_async_tx_descriptor *desc;
+	struct scatterlist *sgl;
+	u32 pio[3];
+
+	/* [1] send out the PIO words */
+	pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
+		| BM_GPMI_CTRL0_WORD_LENGTH
+		| BF_GPMI_CTRL0_CS(mil->current_chip)
+		| BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
+		| BM_GPMI_CTRL0_ADDRESS_INCREMENT
+		| BF_GPMI_CTRL0_XFER_COUNT(mil->command_length);
+	pio[1] = pio[2] = 0;
+	desc = channel->device->device_prep_slave_sg(channel,
+					(struct scatterlist *)pio,
+					ARRAY_SIZE(pio), DMA_NONE, 0);
+	if (!desc) {
+		log("step 1 error");
+		return -1;
+	}
+
+	/* [2] send out the COMMAND + ADDRESS string stored in @buffer */
+	sgl = &mil->cmd_sgl;
+
+	dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
+	sgl->length = mil->command_length;
+	desc = channel->device->device_prep_slave_sg(channel,
+					sgl, 1, DMA_TO_DEVICE, 1);
+	if (!desc) {
+		log("error");
+		return -1;
+	}
+
+	/* [3] submit the DMA */
+	this->dma_type = DMA_FOR_COMMAND;
+	start_dma_without_bch_irq(this, desc);
+	return 0;
+}
+
+static int send_data(struct gpmi_nfc_data *this)
+{
+	struct dma_async_tx_descriptor *desc;
+	struct dma_chan *channel = get_dma_chan(this);
+	struct mil *mil	= &this->mil;
+	uint32_t command_mode;
+	uint32_t address;
+	u32 pio[2];
+
+	/* [1] PIO */
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	pio[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)	|
+		BM_GPMI_CTRL0_WORD_LENGTH			|
+		BF_GPMI_CTRL0_CS(mil->current_chip)		|
+		BF_GPMI_CTRL0_ADDRESS(address)			|
+		BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+	pio[1] = 0;
+	desc = channel->device->device_prep_slave_sg(channel,
+					(struct scatterlist *)pio,
+					ARRAY_SIZE(pio), DMA_NONE, 0);
+	if (!desc) {
+		log("step 1 error");
+		return -1;
+	}
+
+	/* [2] : send DMA request */
+	prepare_data_dma(this, DMA_TO_DEVICE);
+	desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+						1, DMA_TO_DEVICE, 1);
+	if (!desc) {
+		log("step 2 error");
+		return -1;
+	}
+	/* [3] submit the DMA */
+	this->dma_type = DMA_FOR_WRITE_DATA;
+	start_dma_without_bch_irq(this, desc);
+	return 0;
+}
+
+static int read_data(struct gpmi_nfc_data *this)
+{
+	struct dma_async_tx_descriptor *desc;
+	struct dma_chan *channel = get_dma_chan(this);
+	struct mil *mil = &this->mil;
+	u32 pio[2];
+
+	/* [1] : send PIO */
+	pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
+		| BM_GPMI_CTRL0_WORD_LENGTH
+		| BF_GPMI_CTRL0_CS(mil->current_chip)
+		| BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
+		| BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+	pio[1] = 0;
+	desc = channel->device->device_prep_slave_sg(channel,
+					(struct scatterlist *)pio,
+					ARRAY_SIZE(pio), DMA_NONE, 0);
+	if (!desc) {
+		log("step 1 error");
+		return -1;
+	}
+
+	/* [2] : setup DMA buffer */
+	prepare_data_dma(this, DMA_FROM_DEVICE);
+	desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+						1, DMA_FROM_DEVICE, 1);
+	if (!desc) {
+		log("step 2 error");
+		return -1;
+	}
+
+	/* [3] : submit the DMA */
+	this->dma_type = DMA_FOR_READ_DATA;
+	start_dma_without_bch_irq(this, desc);
+	return 0;
+}
+
+static int send_page(struct gpmi_nfc_data *this,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct nfc_geometry  *geo   = &this->nfc_geometry;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+	struct dma_async_tx_descriptor *desc;
+	struct dma_chan *channel = get_dma_chan(this);
+	struct mil *mil = &this->mil;
+	int chip = mil->current_chip;
+	u32 pio[6];
+
+	/* A DMA descriptor that does an ECC page read. */
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	pio[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+		BM_GPMI_CTRL0_WORD_LENGTH                |
+		BF_GPMI_CTRL0_CS(chip)                   |
+		BF_GPMI_CTRL0_ADDRESS(address)           |
+		BF_GPMI_CTRL0_XFER_COUNT(0)              ;
+	pio[1] = 0;
+	pio[2] =
+		BM_GPMI_ECCCTRL_ENABLE_ECC               |
+		BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)     |
+		BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+	pio[3] = geo->page_size_in_bytes;
+	pio[4] = payload;
+	pio[5] = auxiliary;
+
+	desc = channel->device->device_prep_slave_sg(channel,
+					(struct scatterlist *)pio,
+					ARRAY_SIZE(pio), DMA_NONE, 0);
+	if (!desc) {
+		log("step 2 error");
+		return -1;
+	}
+	this->dma_type = DMA_FOR_WRITE_ECC_PAGE;
+	return start_dma_with_bch_irq(this, desc);
+}
+
+static int read_page(struct gpmi_nfc_data *this,
+				dma_addr_t payload, dma_addr_t auxiliary)
+{
+	struct nfc_geometry *geo = &this->nfc_geometry;
+	uint32_t             command_mode;
+	uint32_t             address;
+	uint32_t             ecc_command;
+	uint32_t             buffer_mask;
+
+	struct dma_async_tx_descriptor *desc;
+	struct dma_chan *channel = get_dma_chan(this);
+	struct mil *mil = &this->mil;
+	int chip = mil->current_chip;
+	u32 pio[6];
+
+	/* [1] Wait for the chip to report ready. */
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+		| BM_GPMI_CTRL0_WORD_LENGTH
+		| BF_GPMI_CTRL0_CS(chip)
+		| BF_GPMI_CTRL0_ADDRESS(address)
+		| BF_GPMI_CTRL0_XFER_COUNT(0);
+	pio[1] = 0;
+	desc = channel->device->device_prep_slave_sg(channel,
+				(struct scatterlist *)pio, 2, DMA_NONE, 0);
+	if (!desc) {
+		log("step 1 error");
+		return -1;
+	}
+
+	/* [2] Enable the BCH block and read. */
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+	ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__DECODE;
+	buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
+			| BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+	pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+		| BM_GPMI_CTRL0_WORD_LENGTH
+		| BF_GPMI_CTRL0_CS(chip)
+		| BF_GPMI_CTRL0_ADDRESS(address)
+		| BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes);
+
+	pio[1] = 0;
+	pio[2] =  BM_GPMI_ECCCTRL_ENABLE_ECC
+		| BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
+		| BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
+	pio[3] = geo->page_size_in_bytes;
+	pio[4] = payload;
+	pio[5] = auxiliary;
+	desc = channel->device->device_prep_slave_sg(channel,
+					(struct scatterlist *)pio,
+					ARRAY_SIZE(pio), DMA_NONE, 1);
+	if (!desc) {
+		log("step 2 error");
+		return -1;
+	}
+
+	/* [3] Disable the BCH block */
+	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+	pio[0] =
+		BF_GPMI_CTRL0_COMMAND_MODE(command_mode)              |
+		BM_GPMI_CTRL0_WORD_LENGTH                             |
+		BF_GPMI_CTRL0_CS(chip)                                |
+		BF_GPMI_CTRL0_ADDRESS(address)                        |
+		BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes) ;
+	pio[1] = 0;
+	desc = channel->device->device_prep_slave_sg(channel,
+				(struct scatterlist *)pio, 2, DMA_NONE, 1);
+	if (!desc) {
+		log("step 3 error");
+		return -1;
+	}
+
+	/* [4] submit the DMA */
+	this->dma_type = DMA_FOR_READ_ECC_PAGE;
+	return start_dma_with_bch_irq(this, desc);
+}
+
+/* This structure represents the NFC HAL for this version of the hardware. */
+struct nfc_hal  gpmi_nfc_hal_imx28 = {
+	.version                     = 1,
+	.description                 = "8-chip GPMI and BCH",
+	.max_chip_count              = 8,
+	.max_data_setup_cycles       = (BM_GPMI_TIMING0_DATA_SETUP >>
+						BP_GPMI_TIMING0_DATA_SETUP),
+	.internal_data_setup_in_ns   = 0,
+	.max_sample_delay_factor     = (BM_GPMI_CTRL1_RDN_DELAY >>
+						BP_GPMI_CTRL1_RDN_DELAY),
+	.max_dll_clock_period_in_ns  = 32,
+	.max_dll_delay_in_ns         = 16,
+	.init                        = init_hal_imx28,
+	.set_geometry                = set_geometry,
+	.set_timing                  = set_timing,
+	.get_timing                  = get_timing,
+	.exit                        = exit,
+	.begin                       = begin,
+	.end                         = end,
+	.clear_bch                   = clear_bch,
+	.is_ready                    = is_ready,
+	.send_command                = send_command,
+	.read_data                   = read_data,
+	.send_data                   = send_data,
+	.send_page                   = send_page,
+	.read_page                   = read_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/rom-imx28.c b/drivers/mtd/nand/gpmi-nfc/rom-imx28.c
new file mode 100644
index 0000000..03be07f
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/rom-imx28.c
@@ -0,0 +1,66 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+/* Sets geometry for the Boot ROM Helper. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+	struct gpmi_nfc_platform_data  *pdata    =  this->pdata;
+	struct boot_rom_geometry       *geometry = &this->rom_geometry;
+	int                            error;
+
+	/* Version-independent geometry. */
+	error = gpmi_nfc_rom_helper_set_geometry(this);
+	if (error)
+		return error;
+
+	/*
+	 * Check if the platform data indicates we are to protect the boot area.
+	 */
+	if (!pdata->boot_area_size_in_bytes) {
+		geometry->boot_area_count         = 0;
+		geometry->boot_area_size_in_bytes = 0;
+		return 0;
+	}
+
+	/*
+	 * If control arrives here, we are supposed to set up partitions to
+	 * protect the boot areas. In this version of the ROM, we support only
+	 * one boot area.
+	 */
+	geometry->boot_area_count = 1;
+
+	/*
+	 * Use the platform's boot area size.
+	 */
+	geometry->boot_area_size_in_bytes = pdata->boot_area_size_in_bytes;
+
+	return 0;
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+struct boot_rom_helper  gpmi_nfc_boot_rom_imx28 = {
+	.version                   = 1,
+	.description               = "Single-chip boot area, "
+						"block mark swapping supported",
+	.swap_block_mark           = true,
+	.set_geometry              = set_geometry,
+};
-- 
1.7.0.4

Re: [PATCH 5/7] add GPMI support for imx28

[Artem Bityutskiy]

On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> +#define BF_BCH_CTRL_RSVD5(v)  \
> +               (((v) << 23) & BM_BCH_CTRL_RSVD5) 

Many lines where you used "\" fit 80 lines. Just do not use tabs between
name and value (which is ugly, imo), use a space and then it fits 80
lines. This neater than splitting things on 2 lines.

-- 
Best Regards,
Artem Bityutskiy (Артём Битюцкий)

Re: [PATCH 5/7] add GPMI support for imx28

[Huang Shijie]

Hi:
> On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
>> +#define BF_BCH_CTRL_RSVD5(v)  \
>> +               (((v)<<  23)&  BM_BCH_CTRL_RSVD5)
> Many lines where you used "\" fit 80 lines. Just do not use tabs between
> name and value (which is ugly, imo), use a space and then it fits 80
> lines. This neater than splitting things on 2 lines.
>
Please check the latest version of the driver.
The code has been remove in new version.

Best Regards
Huang Shijie

Re: [PATCH 5/7] add GPMI support for imx28

[Artem Bityutskiy]

On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> +       pio[0] =
> +               BF_GPMI_CTRL0_COMMAND_MODE(command_mode)        |
> +               BM_GPMI_CTRL0_WORD_LENGTH                       |
> +               BF_GPMI_CTRL0_CS(mil->current_chip)             |
> +               BF_GPMI_CTRL0_ADDRESS(address)                  |
> +               BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len); 

Strange way to format the code ...

-- 
Best Regards,
Artem Bityutskiy (Артём Битюцкий)

Re: [PATCH 5/7] add GPMI support for imx28

[Artem Bityutskiy]

On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> +       .description               = "Single-chip boot area, "
> +                                               "block mark swapping
> supported", 

Because you love tabs so much, you have to do this strange splitting of
strings. Just use normal spaces and you'll fit many things in one line.

-- 
Best Regards,
Artem Bityutskiy (Артём Битюцкий)