[PATCH 00/18] mtd/nand/fsmc related modifications

[PATCH 00/18] mtd/nand/fsmc related modifications

[Vipin Kumar]

Hello All,

Please find the nand/fsmc driver modifications
Major modifications include
- DMA support
- Word read/write support to improve performance
- Move platform related things(ALE/CLE) from driver to platfrom files
- Add default partition support for more devices with erase sizes (256KB, 512KB,
		1024KB, 2048KB)
- Bugfixes
	- Read only 512 + 13 bytes for 8bit NAND devices
	- Flip the bit only if the error index is < 4096
	- Fixed data abort inside change_bit()

Armando Visconti (4):
  fsmc_nand.c: Fixed data abort inside change_bit()
  nand/fsmc: Improve the fsmc_correct_data() routine
  fsmc_nand.c: Support of 224-bytes OOB area length
  fsmc/nand: Add support for default partitions for several NAND
    devices

Bhavna Yadav (1):
  mtd/fsmc_nand: ECC1 & ECC4 layout separated for different page sizes

Shiraz Hashim (3):
  nand/fsmc: use ALE and CLE offsets from platform data
  mtd/nand/fsmc: Move ALE, CLE defines to their respective platform
  mtd/fsmc_nand: add pm callbacks to support hibernation

Vipin Kumar (10):
  nand/fsmc: Newly erased page read algorithm implemented
  nand/fsmc: Correct the multiline comment format
  nand/fsmc: Read only 512 + 13 bytes for 8bit NAND devices
  nand/fsmc: Flip the bit only if the error index is < 4096
  nand/fsmc: Initialize the badblockbits to 7
  fsmc/nand: Modify fsmc driver to accept nand timing parameters via
    platform
  fsmc/nand: Use devm routines
  fsmc/nand: Use dev_err to report error scenario
  fsmc/nand: Access the NAND device word by word whenever possible
  fsmc/nand: Add DMA support

 arch/arm/mach-u300/core.c                   |    2 +
 arch/arm/mach-u300/include/mach/u300-regs.h |    5 +
 drivers/mtd/nand/fsmc_nand.c                |  900 ++++++++++++++++++++++-----
 include/linux/mtd/fsmc.h                    |   62 ++-
 4 files changed, 788 insertions(+), 181 deletions(-)

[PATCH 01/18] nand/fsmc: Newly erased page read algorithm implemented

[Vipin Kumar]

A newly erased page contains ff in data as well as spare area. While reading an
erased page, the read out ecc from spare area does not match the ecc generated
by fsmc ecc hardware accelerator. This is because ecc of data ff ff is not ff
ff. This leads to errors when file system erases and reads back the pages to
ensure consistency.

This patch adds a software workaround to ensure that the ecc check is not
performed for erased pages. This problem is solved by checking the number of
bits (in 512 byte data + 13 byte ecc) which are 0. If these number of bits are
less than 8, the page is considered erased and correction algorithm is not tried
on that page

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |   56 +++++++++++++++++++++++++++++++++++++++---
 1 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index e53b760..9c7d9d8 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -391,6 +391,20 @@ static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
 	return 0;
 }
 
+/* Count the number of 0's in buff upto a max of max_bits */
+static int count_written_bits(uint8_t *buff, int size, int max_bits)
+{
+	int k, written_bits = 0;
+
+	for (k = 0; k < size; k++) {
+		written_bits += hweight8(~buff[k]);
+		if (written_bits > max_bits)
+			break;
+	}
+
+	return written_bits;
+}
+
 /*
  * fsmc_read_page_hwecc
  * @mtd:	mtd info structure
@@ -426,7 +440,6 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 	uint8_t *oob = (uint8_t *)&ecc_oob[0];
 
 	for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
-
 		chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
 		chip->ecc.hwctl(mtd, NAND_ECC_READ);
 		chip->read_buf(mtd, p, eccsize);
@@ -447,7 +460,7 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 			j += len;
 		}
 
-		memcpy(&ecc_code[i], oob, 13);
+		memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 
 		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
@@ -475,14 +488,49 @@ static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
 {
 	struct fsmc_nand_data *host = container_of(mtd,
 					struct fsmc_nand_data, mtd);
+	struct nand_chip *chip = mtd->priv;
 	struct fsmc_regs *regs = host->regs_va;
 	unsigned int bank = host->bank;
 	uint16_t err_idx[8];
 	uint64_t ecc_data[2];
 	uint32_t num_err, i;
 
+	num_err = (readl(&regs->bank_regs[bank].sts) >> 10) & 0xF;
+
+	/* no bit flipping */
+	if (likely(num_err == 0))
+		return 0;
+
+	/* too many errors */
+	if (unlikely(num_err > 8)) {
+		/*
+		 * This is a temporary erase check. A newly erased page read
+		 * would result in an ecc error because the oob data is also
+		 * erased to FF and the calculated ecc for an FF data is not
+		 * FF..FF.
+		 * This is a workaround to skip performing correction in case
+		 * data is FF..FF
+		 *
+		 * Logic:
+		 * For every page, each bit written as 0 is counted until these
+		 * number of bits are greater than 8 (the maximum correction
+		 * capability of FSMC for each 512 + 13 bytes)
+		 */
+
+		int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
+		int bits_data = count_written_bits(dat, chip->ecc.size, 8);
+
+		if ((bits_ecc + bits_data) <= 8) {
+			if (bits_data)
+				memset(dat, 0xff, chip->ecc.size);
+			return bits_data;
+		}
+
+		return -EBADMSG;
+	}
+
 	/* The calculated ecc is actually the correction index in data */
-	memcpy(ecc_data, calc_ecc, 13);
+	memcpy(ecc_data, calc_ecc, chip->ecc.bytes);
 
 	/*
 	 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
@@ -513,7 +561,7 @@ static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
 		change_bit(0, (unsigned long *)&err_idx[i]);
 		change_bit(1, (unsigned long *)&err_idx[i]);
 
-		if (err_idx[i] <= 512 * 8) {
+		if (err_idx[i] <= chip->ecc.size * 8) {
 			change_bit(err_idx[i], (unsigned long *)dat);
 			i++;
 		}
-- 
1.7.0.4

Re: [PATCH 01/18] nand/fsmc: Newly erased page read algorithm implemented

[Linus Walleij]

On Wed, Mar 7, 2012 at 12:30 PM, Vipin Kumar <vipin.kumar@st.com> wrote:

> A newly erased page contains ff in data as well as spare area. While reading an
> erased page, the read out ecc from spare area does not match the ecc generated
> by fsmc ecc hardware accelerator. This is because ecc of data ff ff is not ff
> ff. This leads to errors when file system erases and reads back the pages to
> ensure consistency.
>
> This patch adds a software workaround to ensure that the ecc check is not
> performed for erased pages. This problem is solved by checking the number of
> bits (in 512 byte data + 13 byte ecc) which are 0. If these number of bits are
> less than 8, the page is considered erased and correction algorithm is not tried
> on that page
>
> Signed-off-by: Vipin Kumar <vipin.kumar@st.com>

Acked-by: Linus Walleij <linus.walleij@linaro.org>

Thanks,
Linus Walleij

[PATCH 02/18] mtd/fsmc_nand: ECC1 & ECC4 layout separated for different page sizes

[Vipin Kumar]

From: Bhavna Yadav <bhavna.yadav@st.com>

ECC1 & ECC4 layout for NAND of different pages sizes for e.g. 512bytes, 2K, 4K
and 8K are separated. Previously there existed one ECC4 layout for 2K & 4K page
size due to which oob test module available in drivers/mtd/nand/test was failing

Signed-off-by: Bhavna Yadav <bhavna.yadav@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |  176 ++++++++++++++++++++++++++++++++++++++----
 1 files changed, 159 insertions(+), 17 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 9c7d9d8..abbff77 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -34,7 +34,7 @@
 #include <linux/amba/bus.h>
 #include <mtd/mtd-abi.h>
 
-static struct nand_ecclayout fsmc_ecc1_layout = {
+static struct nand_ecclayout fsmc_ecc1_128_layout = {
 	.eccbytes = 24,
 	.eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
 		66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
@@ -50,7 +50,91 @@ static struct nand_ecclayout fsmc_ecc1_layout = {
 	}
 };
 
-static struct nand_ecclayout fsmc_ecc4_lp_layout = {
+static struct nand_ecclayout fsmc_ecc1_64_layout = {
+	.eccbytes = 12,
+	.eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
+	.oobfree = {
+		{.offset = 8, .length = 8},
+		{.offset = 24, .length = 8},
+		{.offset = 40, .length = 8},
+		{.offset = 56, .length = 8},
+	}
+};
+
+static struct nand_ecclayout fsmc_ecc1_16_layout = {
+	.eccbytes = 3,
+	.eccpos = {2, 3, 4},
+	.oobfree = {
+		{.offset = 8, .length = 8},
+	}
+};
+
+/*
+ * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
+ * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
+ * bytes are free for use.
+ */
+static struct nand_ecclayout fsmc_ecc4_256_layout = {
+	.eccbytes = 208,
+	.eccpos = {  2,   3,   4,   5,   6,   7,   8,
+		9,  10,  11,  12,  13,  14,
+		18,  19,  20,  21,  22,  23,  24,
+		25,  26,  27,  28,  29,  30,
+		34,  35,  36,  37,  38,  39,  40,
+		41,  42,  43,  44,  45,  46,
+		50,  51,  52,  53,  54,  55,  56,
+		57,  58,  59,  60,  61,  62,
+		66,  67,  68,  69,  70,  71,  72,
+		73,  74,  75,  76,  77,  78,
+		82,  83,  84,  85,  86,  87,  88,
+		89,  90,  91,  92,  93,  94,
+		98,  99, 100, 101, 102, 103, 104,
+		105, 106, 107, 108, 109, 110,
+		114, 115, 116, 117, 118, 119, 120,
+		121, 122, 123, 124, 125, 126,
+		130, 131, 132, 133, 134, 135, 136,
+		137, 138, 139, 140, 141, 142,
+		146, 147, 148, 149, 150, 151, 152,
+		153, 154, 155, 156, 157, 158,
+		162, 163, 164, 165, 166, 167, 168,
+		169, 170, 171, 172, 173, 174,
+		178, 179, 180, 181, 182, 183, 184,
+		185, 186, 187, 188, 189, 190,
+		194, 195, 196, 197, 198, 199, 200,
+		201, 202, 203, 204, 205, 206,
+		210, 211, 212, 213, 214, 215, 216,
+		217, 218, 219, 220, 221, 222,
+		226, 227, 228, 229, 230, 231, 232,
+		233, 234, 235, 236, 237, 238,
+		242, 243, 244, 245, 246, 247, 248,
+		249, 250, 251, 252, 253, 254
+	},
+	.oobfree = {
+		{.offset = 15, .length = 3},
+		{.offset = 31, .length = 3},
+		{.offset = 47, .length = 3},
+		{.offset = 63, .length = 3},
+		{.offset = 79, .length = 3},
+		{.offset = 95, .length = 3},
+		{.offset = 111, .length = 3},
+		{.offset = 127, .length = 3},
+		{.offset = 143, .length = 3},
+		{.offset = 159, .length = 3},
+		{.offset = 175, .length = 3},
+		{.offset = 191, .length = 3},
+		{.offset = 207, .length = 3},
+		{.offset = 223, .length = 3},
+		{.offset = 239, .length = 3},
+		{.offset = 255, .length = 1}
+	}
+};
+
+/*
+ * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
+ * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
+ * bytes are free for use.
+ */
+static struct nand_ecclayout fsmc_ecc4_128_layout = {
 	.eccbytes = 104,
 	.eccpos = {  2,   3,   4,   5,   6,   7,   8,
 		9,  10,  11,  12,  13,  14,
@@ -82,6 +166,45 @@ static struct nand_ecclayout fsmc_ecc4_lp_layout = {
 };
 
 /*
+ * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
+ * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
+ * bytes are free for use.
+ */
+static struct nand_ecclayout fsmc_ecc4_64_layout = {
+	.eccbytes = 52,
+	.eccpos = {  2,   3,   4,   5,   6,   7,   8,
+		9,  10,  11,  12,  13,  14,
+		18,  19,  20,  21,  22,  23,  24,
+		25,  26,  27,  28,  29,  30,
+		34,  35,  36,  37,  38,  39,  40,
+		41,  42,  43,  44,  45,  46,
+		50,  51,  52,  53,  54,  55,  56,
+		57,  58,  59,  60,  61,  62,
+	},
+	.oobfree = {
+		{.offset = 15, .length = 3},
+		{.offset = 31, .length = 3},
+		{.offset = 47, .length = 3},
+		{.offset = 63, .length = 1},
+	}
+};
+
+/*
+ * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
+ * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
+ * byte is free for use.
+ */
+static struct nand_ecclayout fsmc_ecc4_16_layout = {
+	.eccbytes = 13,
+	.eccpos = { 0,  1,  2,  3,  6,  7, 8,
+		9, 10, 11, 12, 13, 14
+	},
+	.oobfree = {
+		{.offset = 15, .length = 1},
+	}
+};
+
+/*
  * ECC placement definitions in oobfree type format.
  * There are 13 bytes of ecc for every 512 byte block and it has to be read
  * consecutively and immediately after the 512 byte data block for hardware to
@@ -103,16 +226,6 @@ static struct fsmc_eccplace fsmc_ecc4_lp_place = {
 	}
 };
 
-static struct nand_ecclayout fsmc_ecc4_sp_layout = {
-	.eccbytes = 13,
-	.eccpos = { 0,  1,  2,  3,  6,  7, 8,
-		9, 10, 11, 12, 13, 14
-	},
-	.oobfree = {
-		{.offset = 15, .length = 1},
-	}
-};
-
 static struct fsmc_eccplace fsmc_ecc4_sp_place = {
 	.eccplace = {
 		{.offset = 0, .length = 4},
@@ -733,15 +846,44 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	}
 
 	if (AMBA_REV_BITS(host->pid) >= 8) {
-		if (host->mtd.writesize == 512) {
-			nand->ecc.layout = &fsmc_ecc4_sp_layout;
+		switch (host->mtd.oobsize) {
+		case 16:
+			nand->ecc.layout = &fsmc_ecc4_16_layout;
 			host->ecc_place = &fsmc_ecc4_sp_place;
-		} else {
-			nand->ecc.layout = &fsmc_ecc4_lp_layout;
+			break;
+		case 64:
+			nand->ecc.layout = &fsmc_ecc4_64_layout;
+			host->ecc_place = &fsmc_ecc4_lp_place;
+			break;
+		case 128:
+			nand->ecc.layout = &fsmc_ecc4_128_layout;
+			host->ecc_place = &fsmc_ecc4_lp_place;
+			break;
+		case 256:
+			nand->ecc.layout = &fsmc_ecc4_256_layout;
 			host->ecc_place = &fsmc_ecc4_lp_place;
+			break;
+		default:
+			printk(KERN_WARNING "No oob scheme defined for "
+			       "oobsize %d\n", mtd->oobsize);
+			BUG();
 		}
 	} else {
-		nand->ecc.layout = &fsmc_ecc1_layout;
+		switch (host->mtd.oobsize) {
+		case 16:
+			nand->ecc.layout = &fsmc_ecc1_16_layout;
+			break;
+		case 64:
+			nand->ecc.layout = &fsmc_ecc1_64_layout;
+			break;
+		case 128:
+			nand->ecc.layout = &fsmc_ecc1_128_layout;
+			break;
+		default:
+			printk(KERN_WARNING "No oob scheme defined for "
+			       "oobsize %d\n", mtd->oobsize);
+			BUG();
+		}
 	}
 
 	/* Second stage of scan to fill MTD data-structures */
-- 
1.7.0.4

[PATCH 03/18] nand/fsmc: use ALE and CLE offsets from platform data

[Vipin Kumar]

From: Shiraz Hashim <shiraz.hashim@st.com>

ALE and CLE offsets can be different on different devices. Let devices
pass these offsets to the fsmc driver through platform data.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |    9 +++++----
 include/linux/mtd/fsmc.h     |    5 +++++
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index abbff77..4dda9bb 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -729,27 +729,28 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 		goto err_probe1;
 	}
 
-	host->resaddr = request_mem_region(res->start + PLAT_NAND_ALE,
+	host->resaddr = request_mem_region(res->start + pdata->ale_off,
 			resource_size(res), pdev->name);
 	if (!host->resaddr) {
 		ret = -EIO;
 		goto err_probe1;
 	}
 
-	host->addr_va = ioremap(res->start + PLAT_NAND_ALE, resource_size(res));
+	host->addr_va = ioremap(res->start + pdata->ale_off,
+			resource_size(res));
 	if (!host->addr_va) {
 		ret = -EIO;
 		goto err_probe1;
 	}
 
-	host->rescmd = request_mem_region(res->start + PLAT_NAND_CLE,
+	host->rescmd = request_mem_region(res->start + pdata->cle_off,
 			resource_size(res), pdev->name);
 	if (!host->rescmd) {
 		ret = -EIO;
 		goto err_probe1;
 	}
 
-	host->cmd_va = ioremap(res->start + PLAT_NAND_CLE, resource_size(res));
+	host->cmd_va = ioremap(res->start + pdata->cle_off, resource_size(res));
 	if (!host->cmd_va) {
 		ret = -EIO;
 		goto err_probe1;
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h
index 6987995..2cd655f 100644
--- a/include/linux/mtd/fsmc.h
+++ b/include/linux/mtd/fsmc.h
@@ -151,6 +151,11 @@ struct fsmc_nand_platform_data {
 	unsigned int		options;
 	unsigned int		width;
 	unsigned int		bank;
+
+	/* CLE, ALE offsets */
+	unsigned long           cle_off;
+	unsigned long           ale_off;
+
 	void			(*select_bank)(uint32_t bank, uint32_t busw);
 };
 
-- 
1.7.0.4

[PATCH 04/18] mtd/nand/fsmc: Move ALE, CLE defines to their respective platform

[Vipin Kumar]

From: Shiraz Hashim <shiraz.hashim@st.com>

Address Latch Enable (ALE) and Command Latch Enable (CLE) defines are
platform specific and were wrongly put in driver specific fsmc.h file.
Move such defines to their respective platform.

Also instead of relying on fsmc driver, pass ALE, CLE offsets explicitly
from individual platform.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
 arch/arm/mach-u300/core.c                   |    2 ++
 arch/arm/mach-u300/include/mach/u300-regs.h |    5 +++++
 include/linux/mtd/fsmc.h                    |   13 -------------
 3 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 336526a..cb81d3c 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1543,6 +1543,8 @@ static struct fsmc_nand_platform_data nand_platform_data = {
 	.nr_partitions = ARRAY_SIZE(u300_partitions),
 	.options = NAND_SKIP_BBTSCAN,
 	.width = FSMC_NAND_BW8,
+	.ale_off = PLAT_NAND_ALE,
+	.cle_off = PLAT_NAND_CLE,
 };
 
 static struct platform_device nand_device = {
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 035fdc9..b9701fb 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -30,6 +30,11 @@
 /* NFIF */
 #define U300_NAND_IF_PHYS_BASE		0x9f800000
 
+/* ALE, CLE offset for FSMC NAND */
+#define PLAT_NAND_CLE			(1 << 16)
+#define PLAT_NAND_ALE			(1 << 17)
+
+
 /* AHB Peripherals */
 #define U300_AHB_PER_PHYS_BASE		0xa0000000
 #define U300_AHB_PER_VIRT_BASE		0xff010000
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h
index 2cd655f..e877325 100644
--- a/include/linux/mtd/fsmc.h
+++ b/include/linux/mtd/fsmc.h
@@ -26,19 +26,6 @@
 #define FSMC_NAND_BW8		1
 #define FSMC_NAND_BW16		2
 
-/*
- * The placement of the Command Latch Enable (CLE) and
- * Address Latch Enable (ALE) is twisted around in the
- * SPEAR310 implementation.
- */
-#if defined(CONFIG_MACH_SPEAR310)
-#define PLAT_NAND_CLE		(1 << 17)
-#define PLAT_NAND_ALE		(1 << 16)
-#else
-#define PLAT_NAND_CLE		(1 << 16)
-#define PLAT_NAND_ALE		(1 << 17)
-#endif
-
 #define FSMC_MAX_NOR_BANKS	4
 #define FSMC_MAX_NAND_BANKS	4
 
-- 
1.7.0.4

[PATCH 05/18] fsmc_nand.c: Fixed data abort inside change_bit()

[Vipin Kumar]

From: Armando Visconti <armando.visconti@st.com>

Since change_bit() requires a (unsigned int *) as second arg,
the correct definition of err_idx[] array declared as
local variable of fsmc_correct_data() is the following:

	u32 err_idx[8];

Signed-off-by: Armando Visconti <armando.visconti@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 4dda9bb..cfe15a6 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -604,7 +604,7 @@ static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	struct nand_chip *chip = mtd->priv;
 	struct fsmc_regs *regs = host->regs_va;
 	unsigned int bank = host->bank;
-	uint16_t err_idx[8];
+	uint32_t err_idx[8];
 	uint64_t ecc_data[2];
 	uint32_t num_err, i;
 
-- 
1.7.0.4

[PATCH 06/18] nand/fsmc: Improve the fsmc_correct_data() routine

[Vipin Kumar]

From: Armando Visconti <armando.visconti@st.com>

This patch improves the error correction routine for bch8
- Loop only up to number of errors detected
- Improve the error index calculation procedure

Additionally, it also renames the "correct" routine to indicate that it is bch8
specific

Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |   38 +++++++++++++++++---------------------
 1 files changed, 17 insertions(+), 21 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index cfe15a6..5b217f2 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -587,7 +587,7 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 }
 
 /*
- * fsmc_correct_data
+ * fsmc_bch8_correct_data
  * @mtd:	mtd info structure
  * @dat:	buffer of read data
  * @read_ecc:	ecc read from device spare area
@@ -596,7 +596,7 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  * calc_ecc is a 104 bit information containing maximum of 8 error
  * offset informations of 13 bits each in 512 bytes of read data.
  */
-static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
+static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 			     uint8_t *read_ecc, uint8_t *calc_ecc)
 {
 	struct fsmc_nand_data *host = container_of(mtd,
@@ -605,8 +605,8 @@ static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	struct fsmc_regs *regs = host->regs_va;
 	unsigned int bank = host->bank;
 	uint32_t err_idx[8];
-	uint64_t ecc_data[2];
 	uint32_t num_err, i;
+	uint32_t ecc1, ecc2, ecc3, ecc4;
 
 	num_err = (readl(&regs->bank_regs[bank].sts) >> 10) & 0xF;
 
@@ -642,9 +642,6 @@ static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
 		return -EBADMSG;
 	}
 
-	/* The calculated ecc is actually the correction index in data */
-	memcpy(ecc_data, calc_ecc, chip->ecc.bytes);
-
 	/*
 	 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 	 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
@@ -654,20 +651,19 @@ static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	 * uint64_t array and error offset indexes are populated in err_idx
 	 * array
 	 */
-	for (i = 0; i < 8; i++) {
-		if (i == 4) {
-			err_idx[4] = ((ecc_data[1] & 0x1) << 12) | ecc_data[0];
-			ecc_data[1] >>= 1;
-			continue;
-		}
-		err_idx[i] = (ecc_data[i/4] & 0x1FFF);
-		ecc_data[i/4] >>= 13;
-	}
-
-	num_err = (readl(&regs->bank_regs[bank].sts) >> 10) & 0xF;
-
-	if (num_err == 0xF)
-		return -EBADMSG;
+	ecc1 = readl(&regs->bank_regs[bank].ecc1);
+	ecc2 = readl(&regs->bank_regs[bank].ecc2);
+	ecc3 = readl(&regs->bank_regs[bank].ecc3);
+	ecc4 = readl(&regs->bank_regs[bank].sts);
+
+	err_idx[0] = (ecc1 >> 0) & 0x1FFF;
+	err_idx[1] = (ecc1 >> 13) & 0x1FFF;
+	err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
+	err_idx[3] = (ecc2 >> 7) & 0x1FFF;
+	err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
+	err_idx[5] = (ecc3 >> 1) & 0x1FFF;
+	err_idx[6] = (ecc3 >> 14) & 0x1FFF;
+	err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 
 	i = 0;
 	while (num_err--) {
@@ -829,7 +825,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	if (AMBA_REV_BITS(host->pid) >= 8) {
 		nand->ecc.read_page = fsmc_read_page_hwecc;
 		nand->ecc.calculate = fsmc_read_hwecc_ecc4;
-		nand->ecc.correct = fsmc_correct_data;
+		nand->ecc.correct = fsmc_bch8_correct_data;
 		nand->ecc.bytes = 13;
 	} else {
 		nand->ecc.calculate = fsmc_read_hwecc_ecc1;
-- 
1.7.0.4

[PATCH 07/18] fsmc_nand.c: Support of 224-bytes OOB area length

[Vipin Kumar]

From: Armando Visconti <armando.visconti@st.com>

The current patch is required to support EVALSPEAR1340CPU
Revision 2 where a new (ONFI compliant) MT29F16G08 NAND
flash from Micron is present.

This NAND flash device defines a OOB area which is
224 bytes long (oobsize).

Signed-off-by: Armando Visconti <armando.visconti@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |   40 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 5b217f2..4a018d0 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -130,6 +130,42 @@ static struct nand_ecclayout fsmc_ecc4_256_layout = {
 };
 
 /*
+ * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
+ * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
+ * bytes are free for use.
+ */
+static struct nand_ecclayout fsmc_ecc4_224_layout = {
+	.eccbytes = 104,
+	.eccpos = {  2,   3,   4,   5,   6,   7,   8,
+		9,  10,  11,  12,  13,  14,
+		18,  19,  20,  21,  22,  23,  24,
+		25,  26,  27,  28,  29,  30,
+		34,  35,  36,  37,  38,  39,  40,
+		41,  42,  43,  44,  45,  46,
+		50,  51,  52,  53,  54,  55,  56,
+		57,  58,  59,  60,  61,  62,
+		66,  67,  68,  69,  70,  71,  72,
+		73,  74,  75,  76,  77,  78,
+		82,  83,  84,  85,  86,  87,  88,
+		89,  90,  91,  92,  93,  94,
+		98,  99, 100, 101, 102, 103, 104,
+		105, 106, 107, 108, 109, 110,
+		114, 115, 116, 117, 118, 119, 120,
+		121, 122, 123, 124, 125, 126
+	},
+	.oobfree = {
+		{.offset = 15, .length = 3},
+		{.offset = 31, .length = 3},
+		{.offset = 47, .length = 3},
+		{.offset = 63, .length = 3},
+		{.offset = 79, .length = 3},
+		{.offset = 95, .length = 3},
+		{.offset = 111, .length = 3},
+		{.offset = 127, .length = 97}
+	}
+};
+
+/*
  * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
  * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
  * bytes are free for use.
@@ -856,6 +892,10 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 			nand->ecc.layout = &fsmc_ecc4_128_layout;
 			host->ecc_place = &fsmc_ecc4_lp_place;
 			break;
+		case 224:
+			nand->ecc.layout = &fsmc_ecc4_224_layout;
+			host->ecc_place = &fsmc_ecc4_lp_place;
+			break;
 		case 256:
 			nand->ecc.layout = &fsmc_ecc4_256_layout;
 			host->ecc_place = &fsmc_ecc4_lp_place;
-- 
1.7.0.4

[PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Vipin Kumar]

From: Armando Visconti <armando.visconti@st.com>

This patch adds support for default NAND partitions for all devices with erase
size of 256KB, 512KB, 1024KB and 2048KB.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@st.com>
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |  170 ++++++++++++++++++++++++++++++++++++++---
 1 files changed, 157 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 4a018d0..e9b2265 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -284,17 +284,17 @@ static struct mtd_partition partition_info_16KB_blk[] = {
 	},
 	{
 		.name = "U-Boot",
-		.offset = 0x10000,
+		.offset = 4*0x4000,
 		.size = 20*0x4000,
 	},
 	{
 		.name = "Kernel",
-		.offset = 0x60000,
+		.offset = (4+20)*0x4000,
 		.size = 256*0x4000,
 	},
 	{
 		.name = "Root File System",
-		.offset = 0x460000,
+		.offset = (4+20+256)*0x4000,
 		.size = MTDPART_SIZ_FULL,
 	},
 };
@@ -303,6 +303,29 @@ static struct mtd_partition partition_info_16KB_blk[] = {
  * Default partition layout for large page(> 512 bytes) devices
  * Size for "Root file system" is updated in driver based on actual device size
  */
+static struct mtd_partition partition_info_64KB_blk[] = {
+	{
+		.name = "X-loader",
+		.offset = 0,
+		.size = 4*0x10000,
+	},
+	{
+		.name = "U-Boot",
+		.offset = 4*0x10000,
+		.size = 8*0x40000,
+	},
+	{
+		.name = "Kernel",
+		.offset = (4+8)*0x10000,
+		.size = 64*0x40000,
+	},
+	{
+		.name = "Root File System",
+		.offset = (4+8+64)*0x10000,
+		.size = MTDPART_SIZ_FULL,
+	},
+};
+
 static struct mtd_partition partition_info_128KB_blk[] = {
 	{
 		.name = "X-loader",
@@ -311,21 +334,112 @@ static struct mtd_partition partition_info_128KB_blk[] = {
 	},
 	{
 		.name = "U-Boot",
-		.offset = 0x80000,
+		.offset = 4*0x20000,
 		.size = 12*0x20000,
 	},
 	{
 		.name = "Kernel",
-		.offset = 0x200000,
+		.offset = (4+12)*0x20000,
 		.size = 48*0x20000,
 	},
 	{
 		.name = "Root File System",
-		.offset = 0x800000,
+		.offset = (4+12+48)*0x20000,
 		.size = MTDPART_SIZ_FULL,
 	},
 };
 
+static struct mtd_partition partition_info_256KB_blk[] = {
+	{
+		.name = "X-loader",
+		.offset = 0,
+		.size = 4*0x40000,
+	},
+	{
+		.name = "U-Boot",
+		.offset = 4*0x40000,
+		.size = 6*0x40000,
+	},
+	{
+		.name = "Kernel",
+		.offset = (4+6)*0x40000,
+		.size = 24*0x40000,
+	},
+	{
+		.name = "Root File System",
+		.offset = (4+6+24)*0x40000,
+		.size = MTDPART_SIZ_FULL,
+	},
+};
+
+static struct mtd_partition partition_info_512KB_blk[] = {
+	{
+		.name = "X-loader",
+		.offset = 0,
+		.size = 4*0x80000,
+	},
+	{
+		.name = "U-Boot",
+		.offset = 4*0x80000,
+		.size = 6*0x80000,
+	},
+	{
+		.name = "Kernel",
+		.offset = (4+6)*0x80000,
+		.size = 24*0x80000,
+	},
+	{
+		.name = "Root File System",
+		.offset = (4+6+24)*0x80000,
+		.size = MTDPART_SIZ_FULL,
+	},
+};
+
+static struct mtd_partition partition_info_1024KB_blk[] = {
+	{
+		.name = "X-loader",
+		.offset = 0,
+		.size = 4*0x100000,
+	},
+	{
+		.name = "U-Boot",
+		.offset = 4*0x100000,
+		.size = 4*0x100000,
+	},
+	{
+		.name = "Kernel",
+		.offset = (4+4)*0x100000,
+		.size = 12*0x100000,
+	},
+	{
+		.name = "Root File System",
+		.offset = (4+4+12)*0x100000,
+		.size = MTDPART_SIZ_FULL,
+	},
+};
+
+static struct mtd_partition partition_info_2048KB_blk[] = {
+	{
+		.name = "X-loader",
+		.offset = 0,
+		.size = 4*0x200000,
+	},
+	{
+		.name = "U-Boot",
+		.offset = 4*0x200000,
+		.size = 4*0x200000,
+	},
+	{
+		.name = "Kernel",
+		.offset = (4+4)*0x200000,
+		.size = 6*0x200000,
+	},
+	{
+		.name = "Root File System",
+		.offset = (4+4+6)*0x200000,
+		.size = MTDPART_SIZ_FULL,
+	},
+};
 
 /**
  * struct fsmc_nand_data - structure for FSMC NAND device state
@@ -726,6 +840,8 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	struct nand_chip *nand;
 	struct fsmc_regs *regs;
 	struct resource *res;
+	struct mtd_partition *parts;
+	int nr_parts;
 	int ret = 0;
 	u32 pid;
 	int i;
@@ -940,13 +1056,41 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	 * Check for partition info passed
 	 */
 	host->mtd.name = "nand";
-	ret = mtd_device_parse_register(&host->mtd, NULL, 0,
-			host->mtd.size <= 0x04000000 ?
-				partition_info_16KB_blk :
-				partition_info_128KB_blk,
-			host->mtd.size <= 0x04000000 ?
-				ARRAY_SIZE(partition_info_16KB_blk) :
-				ARRAY_SIZE(partition_info_128KB_blk));
+
+	if (host->mtd.erasesize == 0x200000) {
+		parts = partition_info_2048KB_blk;
+		nr_parts = ARRAY_SIZE(partition_info_2048KB_blk);
+
+	} else if (host->mtd.erasesize == 0x100000) {
+		parts = partition_info_1024KB_blk;
+		nr_parts = ARRAY_SIZE(partition_info_1024KB_blk);
+
+	} else if (host->mtd.erasesize == 0x80000) {
+		parts = partition_info_512KB_blk;
+		nr_parts = ARRAY_SIZE(partition_info_512KB_blk);
+
+	} else if (host->mtd.erasesize == 0x40000) {
+		parts = partition_info_256KB_blk;
+		nr_parts = ARRAY_SIZE(partition_info_256KB_blk);
+
+	} else if (host->mtd.erasesize == 0x20000) {
+		parts = partition_info_128KB_blk;
+		nr_parts = ARRAY_SIZE(partition_info_128KB_blk);
+
+	} else if (host->mtd.erasesize == 0x10000) {
+		parts = partition_info_64KB_blk;
+		nr_parts = ARRAY_SIZE(partition_info_64KB_blk);
+
+	} else if (host->mtd.erasesize == 0x4000) {
+		parts = partition_info_16KB_blk;
+		nr_parts = ARRAY_SIZE(partition_info_16KB_blk);
+
+	} else {
+		dev_err(&pdev->dev, "Unrecognized erase size\n");
+		goto err_probe;
+	}
+
+	ret = mtd_device_parse_register(&host->mtd, NULL, 0, parts, nr_parts);
 	if (ret)
 		goto err_probe;
 
-- 
1.7.0.4

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Artem Bityutskiy]

On Wed, 2012-03-07 at 17:00 +0530, Vipin Kumar wrote:
> +static struct mtd_partition partition_info_64KB_blk[] = {
> +	{
> +		.name = "X-loader",
> +		.offset = 0,
> +		.size = 4*0x10000,
> +	},
> +	{
> +		.name = "U-Boot",
> +		.offset = 4*0x10000,
> +		.size = 8*0x40000,
> +	},
> +	{
> +		.name = "Kernel",
> +		.offset = (4+8)*0x10000,
> +		.size = 64*0x40000,
> +	},
> +	{
> +		.name = "Root File System",
> +		.offset = (4+8+64)*0x10000,
> +		.size = MTDPART_SIZ_FULL,
> +	},
> +};

Shouldn't this kind of data come from DT/platform data or cmdline
instead? Does it make sense to have it hard-coded in the driver?

-- 
Best Regards,
Artem Bityutskiy

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Armando Visconti]

On 03/09/2012 02:07 PM, Artem Bityutskiy wrote:
> On Wed, 2012-03-07 at 17:00 +0530, Vipin Kumar wrote:
>> +static struct mtd_partition partition_info_64KB_blk[] = {
>> +	{
>> +		.name = "X-loader",
>> +		.offset = 0,
>> +		.size = 4*0x10000,
>> +	},
>> +	{
>> +		.name = "U-Boot",
>> +		.offset = 4*0x10000,
>> +		.size = 8*0x40000,
>> +	},
>> +	{
>> +		.name = "Kernel",
>> +		.offset = (4+8)*0x10000,
>> +		.size = 64*0x40000,
>> +	},
>> +	{
>> +		.name = "Root File System",
>> +		.offset = (4+8+64)*0x10000,
>> +		.size = MTDPART_SIZ_FULL,
>> +	},
>> +};
>
> Shouldn't this kind of data come from DT/platform data or cmdline
> instead? Does it make sense to have it hard-coded in the driver?
>

These are just the default partitions.
We are passing them also from platform, and it is possible also
from cmdline.

But in case we don't, this is the default.

Shouldn't we treat such a case?

Ciao,
Arm

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Artem Bityutskiy]

On Fri, 2012-03-09 at 15:47 +0100, Armando Visconti wrote:
> On 03/09/2012 02:07 PM, Artem Bityutskiy wrote:
> > On Wed, 2012-03-07 at 17:00 +0530, Vipin Kumar wrote:
> >> +static struct mtd_partition partition_info_64KB_blk[] = {
> >> +	{
> >> +		.name = "X-loader",
> >> +		.offset = 0,
> >> +		.size = 4*0x10000,
> >> +	},
> >> +	{
> >> +		.name = "U-Boot",
> >> +		.offset = 4*0x10000,
> >> +		.size = 8*0x40000,
> >> +	},
> >> +	{
> >> +		.name = "Kernel",
> >> +		.offset = (4+8)*0x10000,
> >> +		.size = 64*0x40000,
> >> +	},
> >> +	{
> >> +		.name = "Root File System",
> >> +		.offset = (4+8+64)*0x10000,
> >> +		.size = MTDPART_SIZ_FULL,
> >> +	},
> >> +};
> >
> > Shouldn't this kind of data come from DT/platform data or cmdline
> > instead? Does it make sense to have it hard-coded in the driver?
> >
> 
> These are just the default partitions.

I thing the default should be "no partitions" instead of a hard-coded
list of partitions tailored to a specific system.

> We are passing them also from platform, and it is possible also
> from cmdline.

Fine, then deleting the defaults should not hurt :-)

-- 
Best Regards,
Artem Bityutskiy

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Armando Visconti]

On 03/09/2012 04:11 PM, Artem Bityutskiy wrote:
> On Fri, 2012-03-09 at 15:47 +0100, Armando Visconti wrote:
>> On 03/09/2012 02:07 PM, Artem Bityutskiy wrote:
>>> On Wed, 2012-03-07 at 17:00 +0530, Vipin Kumar wrote:
>>>> +static struct mtd_partition partition_info_64KB_blk[] = {
>>>> +	{
>>>> +		.name = "X-loader",
>>>> +		.offset = 0,
>>>> +		.size = 4*0x10000,
>>>> +	},
>>>> +	{
>>>> +		.name = "U-Boot",
>>>> +		.offset = 4*0x10000,
>>>> +		.size = 8*0x40000,
>>>> +	},
>>>> +	{
>>>> +		.name = "Kernel",
>>>> +		.offset = (4+8)*0x10000,
>>>> +		.size = 64*0x40000,
>>>> +	},
>>>> +	{
>>>> +		.name = "Root File System",
>>>> +		.offset = (4+8+64)*0x10000,
>>>> +		.size = MTDPART_SIZ_FULL,
>>>> +	},
>>>> +};
>>>
>>> Shouldn't this kind of data come from DT/platform data or cmdline
>>> instead? Does it make sense to have it hard-coded in the driver?
>>>
>>
>> These are just the default partitions.
>
> I thing the default should be "no partitions" instead of a hard-coded
> list of partitions tailored to a specific system.
>
>> We are passing them also from platform, and it is possible also
>> from cmdline.
>
> Fine, then deleting the defaults should not hurt :-)
>

Yes, Artem, I think you are right.
Actually I checked better and I can say that:

   1. We do have the provision to pass the partitions thru pdata and
      cmdline
   2. Nevertheless, we are not passing partitions thru pdata in none
      of our platforms.

I think we need to change this and pass partitions thru pdata.
Vipin, what's your opinion?

Thx,
Arm

-- 
-- "Every step appears to be the unavoidable consequence of the
-- preceding one." (A. Einstein)
-- 
Armando Visconti                  Mobile: (+39) 346 8879146
Senior SW Engineer                Fax:    (+39) 02 93519290
CPG                               Work:   (+39) 02 93519683
Computer System Division          e-mail: armando.visconti@st.com
ST Microelectronics               TINA:   051  4683

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Vipin Kumar]

On 3/13/2012 3:23 PM, Armando VISCONTI wrote:
> On 03/09/2012 04:11 PM, Artem Bityutskiy wrote:
>> On Fri, 2012-03-09 at 15:47 +0100, Armando Visconti wrote:
>>> On 03/09/2012 02:07 PM, Artem Bityutskiy wrote:
>>>> On Wed, 2012-03-07 at 17:00 +0530, Vipin Kumar wrote:
>>>>> +static struct mtd_partition partition_info_64KB_blk[] = {
>>>>> +	{
>>>>> +		.name = "X-loader",
>>>>> +		.offset = 0,
>>>>> +		.size = 4*0x10000,
>>>>> +	},
>>>>> +	{
>>>>> +		.name = "U-Boot",
>>>>> +		.offset = 4*0x10000,
>>>>> +		.size = 8*0x40000,
>>>>> +	},
>>>>> +	{
>>>>> +		.name = "Kernel",
>>>>> +		.offset = (4+8)*0x10000,
>>>>> +		.size = 64*0x40000,
>>>>> +	},
>>>>> +	{
>>>>> +		.name = "Root File System",
>>>>> +		.offset = (4+8+64)*0x10000,
>>>>> +		.size = MTDPART_SIZ_FULL,
>>>>> +	},
>>>>> +};
>>>>
>>>> Shouldn't this kind of data come from DT/platform data or cmdline
>>>> instead? Does it make sense to have it hard-coded in the driver?
>>>>
>>>
>>> These are just the default partitions.
>>
>> I thing the default should be "no partitions" instead of a hard-coded
>> list of partitions tailored to a specific system.
>>
>>> We are passing them also from platform, and it is possible also
>>> from cmdline.
>>
>> Fine, then deleting the defaults should not hurt :-)
>>
>
> Yes, Artem, I think you are right.
> Actually I checked better and I can say that:
>
>     1. We do have the provision to pass the partitions thru pdata and
>        cmdline
>     2. Nevertheless, we are not passing partitions thru pdata in none
>        of our platforms.
>
> I think we need to change this and pass partitions thru pdata.
> Vipin, what's your opinion?
>

Yes, I was thinking on the same lines. Infact I have prepared the 
patches and only going through a basic testing before sending the 
patches to mainline

Regards
Vipin

> Thx,
> Arm
>

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Linus Walleij]

On Tue, Mar 13, 2012 at 10:53 AM, Armando Visconti
<armando.visconti@st.com> wrote:

> Actually I checked better and I can say that:
>
>  1. We do have the provision to pass the partitions thru pdata and
>     cmdline
>  2. Nevertheless, we are not passing partitions thru pdata in none
>     of our platforms.
>
> I think we need to change this and pass partitions thru pdata.

This would be cleaner, actually I am using the same driver on the
U300 (also for Nomadik the day I find some time to adopt it)
and I get the default partitions from some SPEAr platform
currently, I think I should rather get some warning message from
the driver or MTD core like "you haven't defined any partitions".

Linus Walleij

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Linus Walleij]

On Tue, Mar 13, 2012 at 12:56 PM, Linus Walleij
<linus.walleij@linaro.org> wrote:
> On Tue, Mar 13, 2012 at 10:53 AM, Armando Visconti
>
>> Actually I checked better and I can say that:
>>
>>  1. We do have the provision to pass the partitions thru pdata and
>>     cmdline

Oh. no, wait. The driver is broken, I just realized:
commit 0d04eda1430e9a796214bee644b7e05d99cfe613
"mtd: fsmc_nand.c: use mtd_device_parse_register" broke
the ability to pass in partitions from platform data and I did
not realize until now. :-/

> (...) and I get the default partitions from some SPEAr platform
> currently,

This is just because of the above bug.

I'll fix!

Yours,
Linus Walleij

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Artem Bityutskiy]

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On Tue, 2012-03-13 at 13:39 +0100, Linus Walleij wrote:
> On Tue, Mar 13, 2012 at 12:56 PM, Linus Walleij
> <linus.walleij@linaro.org> wrote:
> > On Tue, Mar 13, 2012 at 10:53 AM, Armando Visconti
> >
> >> Actually I checked better and I can say that:
> >>
> >>  1. We do have the provision to pass the partitions thru pdata and
> >>     cmdline
> 
> Oh. no, wait. The driver is broken, I just realized:
> commit 0d04eda1430e9a796214bee644b7e05d99cfe613
> "mtd: fsmc_nand.c: use mtd_device_parse_register" broke
> the ability to pass in partitions from platform data and I did
> not realize until now. :-/
> 
> > (...) and I get the default partitions from some SPEAr platform
> > currently,
> 
> This is just because of the above bug.

Yeah, there were many bug-fixes like for this stuff. Please, base your
patch on top of the l2-mtd.git tree:

git://git.infradead.org/users/dedekind/l2-mtd.git

and add

Cc: stable@kernel.org [3.2+]

Thanks!

-- 
Best Regards,
Artem Bityutskiy

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Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Stefan Roese]

On Tuesday 13 March 2012 13:39:32 Linus Walleij wrote:
> > (...) and I get the default partitions from some SPEAr platform
> > currently,
> 
> This is just because of the above bug.
> 
> I'll fix!

I already sent a fix for this:

mtd: fsmc_nand.c: Partition info from pdata overrides driver defaults

Thanks,
Stefan

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Linus Walleij]

On Tue, Mar 13, 2012 at 1:53 PM, Stefan Roese <sr@denx.de> wrote:
> On Tuesday 13 March 2012 13:39:32 Linus Walleij wrote:
>> > (...) and I get the default partitions from some SPEAr platform
>> > currently,
>>
>> This is just because of the above bug.
>>
>> I'll fix!
>
> I already sent a fix for this:
>
> mtd: fsmc_nand.c: Partition info from pdata overrides driver defaults

Oh sorry I was coding too quickly. Missed it previously.
Thanks for fixing this.

Artem, forget my patch if you like, if you already have Stefan's patch
applied, please add Cc: stable@kernel.org on it because I'm using
this driver...

Yours,
Linus Walleij

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Artem Bityutskiy]

[-- Attachment #1: Type: text/plain, Size: 1531 bytes --]

On Tue, 2012-03-13 at 14:01 +0100, Linus Walleij wrote:
> On Tue, Mar 13, 2012 at 1:53 PM, Stefan Roese <sr@denx.de> wrote:
> > On Tuesday 13 March 2012 13:39:32 Linus Walleij wrote:
> >> > (...) and I get the default partitions from some SPEAr platform
> >> > currently,
> >>
> >> This is just because of the above bug.
> >>
> >> I'll fix!
> >
> > I already sent a fix for this:
> >
> > mtd: fsmc_nand.c: Partition info from pdata overrides driver defaults
> 
> Oh sorry I was coding too quickly. Missed it previously.
> Thanks for fixing this.
> 
> Artem, forget my patch if you like, if you already have Stefan's patch
> applied, please add Cc: stable@kernel.org on it because I'm using
> this driver...

I somehow missed Stefan's patch, and was not pinged, unfortunately. I
see it in my mailbox, but it does not apply anymore because it conflicts
with patches from st.com which I applied recently.

Stefan, would you re-send a new version and add:

Cc: stable@kernel.org [3.2+]

Sorry for missing your patch.

Additional notes about -stable.

When Greg will try to push this patch to -stable, the patch won't apply,
and he traditionally sends an e-mail in such cases with something like
"if you care, send me an applicable version, or I'll drop this patch".
He usually adds people who signed-off the patch to CC. So to make sure
Linus W. gets this patch in -stable, we need to add his Signed-off by as
well, and then he'll need to respond to Greg.

-- 
Best Regards,
Artem Bityutskiy

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Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Stefan Roese]

Artem,

On Tuesday 13 March 2012 14:19:40 Artem Bityutskiy wrote:
> > Oh sorry I was coding too quickly. Missed it previously.
> > Thanks for fixing this.
> > 
> > Artem, forget my patch if you like, if you already have Stefan's patch
> > applied, please add Cc: stable@kernel.org on it because I'm using
> > this driver...
> 
> I somehow missed Stefan's patch, and was not pinged, unfortunately. I
> see it in my mailbox, but it does not apply anymore because it conflicts
> with patches from st.com which I applied recently.
> 
> Stefan, would you re-send a new version and add:
>
> Cc: stable@kernel.org [3.2+]
> 
> Sorry for missing your patch.

No problem.

But the patch still applies clean onto kernel.org. I suspect that the 
conflicts are with your l2-mtd.git tree, correct? Will you push the l2 tree 
still into v3.3? If not, then this patch could be applied as is into mainline.

I'm confused. ;) Please advise.
 
Thanks,
Stefan

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Artem Bityutskiy]

[-- Attachment #1: Type: text/plain, Size: 461 bytes --]

On Tue, 2012-03-13 at 14:36 +0100, Stefan Roese wrote:
> No problem.
> 
> But the patch still applies clean onto kernel.org.

OK.

>  I suspect that the 
> conflicts are with your l2-mtd.git tree, correct?

Right.

>  Will you push the l2 tree 
> still into v3.3? 

No.

> If not, then this patch could be applied as is into mainline.

Well, if you can make this happen, fine, but I cannot help here.

-- 
Best Regards,
Artem Bityutskiy

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Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Vipin Kumar]

On 3/13/2012 7:37 PM, Artem Bityutskiy wrote:
> On Tue, 2012-03-13 at 14:36 +0100, Stefan Roese wrote:
>> No problem.
>>
>> But the patch still applies clean onto kernel.org.
>
> OK.
>

I am sorry for pitching in too late. It seems that Stefan, Linus and I 
have sent the same patch (in the same order) achieving same result. It 
was a mistake on my part to not have rebased on either of these patches.

Artem, please suggest how to proceed as there would be conflicts if you 
try to apply Stefan's patch before my patch-set

>>   I suspect that the
>> conflicts are with your l2-mtd.git tree, correct?
>
> Right.
>
>>   Will you push the l2 tree
>> still into v3.3?
>
> No.
>

So, these changes would be merged in next release
Am I right

Regards
Vipin

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Stefan Roese]

On Wednesday 14 March 2012 07:33:36 Vipin Kumar wrote:
> On 3/13/2012 7:37 PM, Artem Bityutskiy wrote:
> > On Tue, 2012-03-13 at 14:36 +0100, Stefan Roese wrote:
> >> No problem.
> >> 
> >> But the patch still applies clean onto kernel.org.
> > 
> > OK.
> 
> I am sorry for pitching in too late. It seems that Stefan, Linus and I
> have sent the same patch (in the same order) achieving same result. It
> was a mistake on my part to not have rebased on either of these patches.
> 
> Artem, please suggest how to proceed as there would be conflicts if you
> try to apply Stefan's patch before my patch-set

I suggest to just drop my patch then, since I still have to rebase it on-top 
of the l2 tree. So easiest is most likely, to apply Vipins's patchset now.

Okay?

Thanks,
Stefan

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Vipin Kumar]

On 3/14/2012 12:40 PM, Stefan Roese wrote:
> On Wednesday 14 March 2012 07:33:36 Vipin Kumar wrote:
>> On 3/13/2012 7:37 PM, Artem Bityutskiy wrote:
>>> On Tue, 2012-03-13 at 14:36 +0100, Stefan Roese wrote:
>>>> No problem.
>>>>
>>>> But the patch still applies clean onto kernel.org.
>>>
>>> OK.
>>
>> I am sorry for pitching in too late. It seems that Stefan, Linus and I
>> have sent the same patch (in the same order) achieving same result. It
>> was a mistake on my part to not have rebased on either of these patches.
>>
>> Artem, please suggest how to proceed as there would be conflicts if you
>> try to apply Stefan's patch before my patch-set
>
> I suggest to just drop my patch then, since I still have to rebase it on-top
> of the l2 tree. So easiest is most likely, to apply Vipins's patchset now.
>
> Okay?
>

Thanks Stefan

> Thanks,
> Stefan

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Linus Walleij]

On Wed, Mar 14, 2012 at 8:10 AM, Stefan Roese <sr@denx.de> wrote:
> On Wednesday 14 March 2012 07:33:36 Vipin Kumar wrote:
>> Artem, please suggest how to proceed as there would be conflicts if you
>> try to apply Stefan's patch before my patch-set
>
> I suggest to just drop my patch then, since I still have to rebase it on-top
> of the l2 tree. So easiest is most likely, to apply Vipins's patchset now.

I agree, use Vipin's stuff!

Yours,
Linus Walleij

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Artem Bityutskiy]

[-- Attachment #1: Type: text/plain, Size: 685 bytes --]

On Wed, 2012-03-14 at 09:57 +0100, Linus Walleij wrote:
> On Wed, Mar 14, 2012 at 8:10 AM, Stefan Roese <sr@denx.de> wrote:
> > On Wednesday 14 March 2012 07:33:36 Vipin Kumar wrote:
> >> Artem, please suggest how to proceed as there would be conflicts if you
> >> try to apply Stefan's patch before my patch-set
> >
> > I suggest to just drop my patch then, since I still have to rebase it on-top
> > of the l2 tree. So easiest is most likely, to apply Vipins's patchset now.
> 
> I agree, use Vipin's stuff!

Could you guys signe-off that patch to make sure you get Greg's
complaint later on and send him the version for -stable?

-- 
Best Regards,
Artem Bityutskiy

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Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Linus Walleij]

On Wed, Mar 14, 2012 at 12:02 PM, Artem Bityutskiy <dedekind1@gmail.com> wrote:
> On Wed, 2012-03-14 at 09:57 +0100, Linus Walleij wrote:
>>
>> I agree, use Vipin's stuff!
>
> Could you guys signe-off that patch to make sure you get Greg's
> complaint later on and send him the version for -stable?

OK I think I understand what you want... I'll reply to Vipin's
patch with SoB?

Linus

Re: [PATCH 08/18] fsmc/nand: Add support for default partitions for several NAND devices

[Stefan Roese]

On Tuesday 13 March 2012 12:56:47 Linus Walleij wrote:
> On Tue, Mar 13, 2012 at 10:53 AM, Armando Visconti
> 
> <armando.visconti@st.com> wrote:
> > Actually I checked better and I can say that:
> > 
> >  1. We do have the provision to pass the partitions thru pdata and
> >     cmdline
> >  2. Nevertheless, we are not passing partitions thru pdata in none
> >     of our platforms.
> > 
> > I think we need to change this and pass partitions thru pdata.
> 
> This would be cleaner, actually I am using the same driver on the
> U300 (also for Nomadik the day I find some time to adopt it)
> and I get the default partitions from some SPEAr platform
> currently, I think I should rather get some warning message from
> the driver or MTD core like "you haven't defined any partitions".

I have a patch in my queue to add device-tree support to the FSMC driver. This 
will also add parsing partition via DT. As SPEAr currently doesn't support 
this driver in mainline, I suggest not to add pdata support to those SPEAr 
platforms, but move to DT directly.

Thanks,
Stefan

[PATCH 09/18] nand/fsmc: Correct the multiline comment format

[Vipin Kumar]

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index e9b2265..29be94c 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -713,10 +713,10 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 			group++;
 
 			/*
-			* length is intentionally kept a higher multiple of 2
-			* to read at least 13 bytes even in case of 16 bit NAND
-			* devices
-			*/
+			 * length is intentionally kept a higher multiple of 2
+			 * to read at least 13 bytes even in case of 16 bit NAND
+			 * devices
+			 */
 			len = roundup(len, 2);
 			chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 			chip->read_buf(mtd, oob + j, len);
-- 
1.7.0.4

[PATCH 10/18] nand/fsmc: Read only 512 + 13 bytes for 8bit NAND devices

[Vipin Kumar]

The ECC logic of FSMC works on 512 bytes data + 13 bytes ECC to generate error
indices of upto 8 incorrect bits. The FSMC driver reads 14 instead of 13 oob
bytes to accommodate for 16 bit device as well.

Unfortunately, the internal ecc state machine gets corrupted for 8 bit devices
reading 512 + 14 bytes of data resulting in error indices not getting reported.

Fix this by reading 14 bytes only for 16 bit devices

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 29be94c..5bc6410 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -717,7 +717,9 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 			 * to read at least 13 bytes even in case of 16 bit NAND
 			 * devices
 			 */
-			len = roundup(len, 2);
+			if (chip->options & NAND_BUSWIDTH_16)
+				len = roundup(len, 2);
+
 			chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 			chip->read_buf(mtd, oob + j, len);
 			j += len;
-- 
1.7.0.4

[PATCH 11/18] nand/fsmc: Flip the bit only if the error index is < 4096

[Vipin Kumar]

ECC can correct upto 8 bits in 512 bytes data + 13 bytes ecc. This means that
the algorithm can correct a max of 8 bits in 4200 bits ie the error indices can
be from 0 to 4199. Of these 0 to 4095 are for data and 4096 to 4199 for ecc.

The driver flips the bit only if the index is <= 4096. This is a bug since the
data bits are only from 0 to 4095.

This patch modifies the check as < 4096

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 5bc6410..9e9d90b 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -822,7 +822,7 @@ static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 		change_bit(0, (unsigned long *)&err_idx[i]);
 		change_bit(1, (unsigned long *)&err_idx[i]);
 
-		if (err_idx[i] <= chip->ecc.size * 8) {
+		if (err_idx[i] < chip->ecc.size * 8) {
 			change_bit(err_idx[i], (unsigned long *)dat);
 			i++;
 		}
-- 
1.7.0.4

[PATCH 12/18] nand/fsmc: Initialize the badblockbits to 7

[Vipin Kumar]

Ideally, the block should have 0xff written on the bad block position. Any value
other than 0xff implies a bad block. In practical situations, there can be
bit flips in the oob area as well which means that a block with 0x7f being read
at bad block position may imply a bad block but it is infact only a bit flip in
the bad block byte.

To resolve this problem, the block is marked as good if number of high bits is
greater than or equal to badblockbits (initialized to 7)

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 9e9d90b..8b5000c 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -970,6 +970,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	nand->ecc.size = 512;
 	nand->options = pdata->options;
 	nand->select_chip = fsmc_select_chip;
+	nand->badblockbits = 7;
 
 	if (pdata->width == FSMC_NAND_BW16)
 		nand->options |= NAND_BUSWIDTH_16;
-- 
1.7.0.4

[PATCH 13/18] mtd/fsmc_nand: add pm callbacks to support hibernation

[Vipin Kumar]

From: Shiraz Hashim <shiraz.hashim@st.com>

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 8b5000c..51add35 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -550,7 +550,7 @@ static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  * This routine initializes timing parameters related to NAND memory access in
  * FSMC registers
  */
-static void __init fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
+static void fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
 				   uint32_t busw)
 {
 	uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
@@ -1175,15 +1175,15 @@ static int fsmc_nand_suspend(struct device *dev)
 static int fsmc_nand_resume(struct device *dev)
 {
 	struct fsmc_nand_data *host = dev_get_drvdata(dev);
-	if (host)
+	if (host) {
 		clk_enable(host->clk);
+		fsmc_nand_setup(host->regs_va, host->bank,
+				host->nand.options & NAND_BUSWIDTH_16);
+	}
 	return 0;
 }
 
-static const struct dev_pm_ops fsmc_nand_pm_ops = {
-	.suspend = fsmc_nand_suspend,
-	.resume = fsmc_nand_resume,
-};
+static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
 #endif
 
 static struct platform_driver fsmc_nand_driver = {
-- 
1.7.0.4

[PATCH 14/18] fsmc/nand: Modify fsmc driver to accept nand timing parameters via platform

[Vipin Kumar]

FSMC controllers provide registers to program the required timing values for
attached NAND device. The timing values used until now are relaxed and should
work for all devices.

Although, for read/write performance improvements, the fsmc nand driver should
accept nand timings as a platform data and program the timing parameters into
fsmc registers accordingly.

This patch implements this modification. Additionally, it programs the default
timing parameters if these are not passed via platform data.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |   41 +++++++++++++++++++++++++++++++++--------
 include/linux/mtd/fsmc.h     |   34 ++++++++++++++++++++++++++++------
 2 files changed, 61 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 51add35..7b2e66c 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -471,6 +471,8 @@ struct fsmc_nand_data {
 	struct resource		*resaddr;
 	struct resource		*resdata;
 
+	struct fsmc_nand_timings *dev_timings;
+
 	void __iomem		*data_va;
 	void __iomem		*cmd_va;
 	void __iomem		*addr_va;
@@ -551,21 +553,41 @@ static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  * FSMC registers
  */
 static void fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
-				   uint32_t busw)
+			   uint32_t busw, struct fsmc_nand_timings *timings)
 {
 	uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
+	uint32_t tclr, tar, thiz, thold, twait, tset;
+	struct fsmc_nand_timings *tims;
+	struct fsmc_nand_timings default_timings = {
+		.tclr	= FSMC_TCLR_1,
+		.tar	= FSMC_TAR_1,
+		.thiz	= FSMC_THIZ_1,
+		.thold	= FSMC_THOLD_4,
+		.twait	= FSMC_TWAIT_6,
+		.tset	= FSMC_TSET_0,
+	};
+
+	if (timings)
+		tims = timings;
+	else
+		tims = &default_timings;
+
+	tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
+	tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
+	thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
+	thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
+	twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
+	tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 
 	if (busw)
 		writel(value | FSMC_DEVWID_16, &regs->bank_regs[bank].pc);
 	else
 		writel(value | FSMC_DEVWID_8, &regs->bank_regs[bank].pc);
 
-	writel(readl(&regs->bank_regs[bank].pc) | FSMC_TCLR_1 | FSMC_TAR_1,
+	writel(readl(&regs->bank_regs[bank].pc) | tclr | tar,
 	       &regs->bank_regs[bank].pc);
-	writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
-	       &regs->bank_regs[bank].comm);
-	writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
-	       &regs->bank_regs[bank].attrib);
+	writel(thiz | thold | twait | tset, &regs->bank_regs[bank].comm);
+	writel(thiz | thold | twait | tset, &regs->bank_regs[bank].attrib);
 }
 
 /*
@@ -951,6 +973,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 
 	host->bank = pdata->bank;
 	host->select_chip = pdata->select_bank;
+	host->dev_timings = pdata->nand_timings;
 	regs = host->regs_va;
 
 	/* Link all private pointers */
@@ -975,7 +998,8 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	if (pdata->width == FSMC_NAND_BW16)
 		nand->options |= NAND_BUSWIDTH_16;
 
-	fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16);
+	fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16,
+			host->dev_timings);
 
 	if (AMBA_REV_BITS(host->pid) >= 8) {
 		nand->ecc.read_page = fsmc_read_page_hwecc;
@@ -1178,7 +1202,8 @@ static int fsmc_nand_resume(struct device *dev)
 	if (host) {
 		clk_enable(host->clk);
 		fsmc_nand_setup(host->regs_va, host->bank,
-				host->nand.options & NAND_BUSWIDTH_16);
+				host->nand.options & NAND_BUSWIDTH_16,
+				host->dev_timings);
 	}
 	return 0;
 }
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h
index e877325..c4ac07a 100644
--- a/include/linux/mtd/fsmc.h
+++ b/include/linux/mtd/fsmc.h
@@ -90,17 +90,29 @@ struct fsmc_regs {
 #define FSMC_ECCEN		(1 << 6)
 #define FSMC_ECCPLEN_512	(0 << 7)
 #define FSMC_ECCPLEN_256	(1 << 7)
-#define FSMC_TCLR_1		(1 << 9)
-#define FSMC_TAR_1		(1 << 13)
+#define FSMC_TCLR_1		(1)
+#define FSMC_TCLR_SHIFT		(9)
+#define FSMC_TCLR_MASK		(0xF)
+#define FSMC_TAR_1		(1)
+#define FSMC_TAR_SHIFT		(13)
+#define FSMC_TAR_MASK		(0xF)
 
 /* sts register definitions */
 #define FSMC_CODE_RDY		(1 << 15)
 
 /* comm register definitions */
-#define FSMC_TSET_0		(0 << 0)
-#define FSMC_TWAIT_6		(6 << 8)
-#define FSMC_THOLD_4		(4 << 16)
-#define FSMC_THIZ_1		(1 << 24)
+#define FSMC_TSET_0		0
+#define FSMC_TSET_SHIFT		0
+#define FSMC_TSET_MASK		0xFF
+#define FSMC_TWAIT_6		6
+#define FSMC_TWAIT_SHIFT	8
+#define FSMC_TWAIT_MASK		0xFF
+#define FSMC_THOLD_4		4
+#define FSMC_THOLD_SHIFT	16
+#define FSMC_THOLD_MASK		0xFF
+#define FSMC_THIZ_1		1
+#define FSMC_THIZ_SHIFT		24
+#define FSMC_THIZ_MASK		0xFF
 
 /*
  * There are 13 bytes of ecc for every 512 byte block in FSMC version 8
@@ -120,6 +132,15 @@ struct fsmc_eccplace {
 	struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
 };
 
+struct fsmc_nand_timings {
+	uint8_t tclr;
+	uint8_t tar;
+	uint8_t thiz;
+	uint8_t thold;
+	uint8_t twait;
+	uint8_t tset;
+};
+
 /**
  * fsmc_nand_platform_data - platform specific NAND controller config
  * @partitions: partition table for the platform, use a default fallback
@@ -133,6 +154,7 @@ struct fsmc_eccplace {
  * this may be set to NULL
  */
 struct fsmc_nand_platform_data {
+	struct fsmc_nand_timings *nand_timings;
 	struct mtd_partition	*partitions;
 	unsigned int		nr_partitions;
 	unsigned int		options;
-- 
1.7.0.4

[PATCH 15/18] fsmc/nand: Use devm routines

[Vipin Kumar]

fsmc_nand driver currently uses normal kzalloc, request_mem etc routines. This
patch replaces these routines with devm_kzalloc and devm_request_mem_region etc.
Consequently, the error and driver removal scenarios are curtailed.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |  134 +++++++++++++----------------------------
 1 files changed, 43 insertions(+), 91 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 7b2e66c..08aa93e 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -466,11 +466,6 @@ struct fsmc_nand_data {
 	unsigned int		bank;
 	struct clk		*clk;
 
-	struct resource		*resregs;
-	struct resource		*rescmd;
-	struct resource		*resaddr;
-	struct resource		*resdata;
-
 	struct fsmc_nand_timings *dev_timings;
 
 	void __iomem		*data_va;
@@ -876,88 +871,81 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	}
 
 	/* Allocate memory for the device structure (and zero it) */
-	host = kzalloc(sizeof(*host), GFP_KERNEL);
+	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 	if (!host) {
 		dev_err(&pdev->dev, "failed to allocate device structure\n");
 		return -ENOMEM;
 	}
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
-	if (!res) {
-		ret = -EIO;
-		goto err_probe1;
-	}
+	if (!res)
+		return -EINVAL;
 
-	host->resdata = request_mem_region(res->start, resource_size(res),
-			pdev->name);
-	if (!host->resdata) {
-		ret = -EIO;
-		goto err_probe1;
+	if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
+				pdev->name)) {
+		dev_err(&pdev->dev, "Failed to get memory data resourse\n");
+		return -ENOENT;
 	}
 
-	host->data_va = ioremap(res->start, resource_size(res));
+	host->data_va = devm_ioremap(&pdev->dev, res->start,
+			resource_size(res));
 	if (!host->data_va) {
-		ret = -EIO;
-		goto err_probe1;
+		dev_err(&pdev->dev, "data ioremap failed\n");
+		return -ENOMEM;
 	}
 
-	host->resaddr = request_mem_region(res->start + pdata->ale_off,
-			resource_size(res), pdev->name);
-	if (!host->resaddr) {
-		ret = -EIO;
-		goto err_probe1;
+	if (!devm_request_mem_region(&pdev->dev, res->start + pdata->ale_off,
+			resource_size(res), pdev->name)) {
+		dev_err(&pdev->dev, "Failed to get memory ale resourse\n");
+		return -ENOENT;
 	}
 
-	host->addr_va = ioremap(res->start + pdata->ale_off,
+	host->addr_va = devm_ioremap(&pdev->dev, res->start + pdata->ale_off,
 			resource_size(res));
 	if (!host->addr_va) {
-		ret = -EIO;
-		goto err_probe1;
+		dev_err(&pdev->dev, "ale ioremap failed\n");
+		return -ENOMEM;
 	}
 
-	host->rescmd = request_mem_region(res->start + pdata->cle_off,
-			resource_size(res), pdev->name);
-	if (!host->rescmd) {
-		ret = -EIO;
-		goto err_probe1;
+	if (!devm_request_mem_region(&pdev->dev, res->start + pdata->cle_off,
+			resource_size(res), pdev->name)) {
+		dev_err(&pdev->dev, "Failed to get memory cle resourse\n");
+		return -ENOENT;
 	}
 
-	host->cmd_va = ioremap(res->start + pdata->cle_off, resource_size(res));
+	host->cmd_va = devm_ioremap(&pdev->dev, res->start + pdata->cle_off,
+			resource_size(res));
 	if (!host->cmd_va) {
-		ret = -EIO;
-		goto err_probe1;
+		dev_err(&pdev->dev, "ale ioremap failed\n");
+		return -ENOMEM;
 	}
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
-	if (!res) {
-		ret = -EIO;
-		goto err_probe1;
-	}
+	if (!res)
+		return -EINVAL;
 
-	host->resregs = request_mem_region(res->start, resource_size(res),
-			pdev->name);
-	if (!host->resregs) {
-		ret = -EIO;
-		goto err_probe1;
+	if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
+			pdev->name)) {
+		dev_err(&pdev->dev, "Failed to get memory regs resourse\n");
+		return -ENOENT;
 	}
 
-	host->regs_va = ioremap(res->start, resource_size(res));
+	host->regs_va = devm_ioremap(&pdev->dev, res->start,
+			resource_size(res));
 	if (!host->regs_va) {
-		ret = -EIO;
-		goto err_probe1;
+		dev_err(&pdev->dev, "regs ioremap failed\n");
+		return -ENOMEM;
 	}
 
 	host->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(host->clk)) {
 		dev_err(&pdev->dev, "failed to fetch block clock\n");
-		ret = PTR_ERR(host->clk);
-		host->clk = NULL;
-		goto err_probe1;
+		return PTR_ERR(host->clk);
 	}
 
 	ret = clk_enable(host->clk);
 	if (ret)
-		goto err_probe1;
+		goto err_clk_enable;
 
 	/*
 	 * This device ID is actually a common AMBA ID as used on the
@@ -1018,7 +1006,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	if (nand_scan_ident(&host->mtd, 1, NULL)) {
 		ret = -ENXIO;
 		dev_err(&pdev->dev, "No NAND Device found!\n");
-		goto err_probe;
+		goto err_scan_ident;
 	}
 
 	if (AMBA_REV_BITS(host->pid) >= 8) {
@@ -1126,32 +1114,10 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	return 0;
 
 err_probe:
+err_scan_ident:
 	clk_disable(host->clk);
-err_probe1:
-	if (host->clk)
-		clk_put(host->clk);
-	if (host->regs_va)
-		iounmap(host->regs_va);
-	if (host->resregs)
-		release_mem_region(host->resregs->start,
-				resource_size(host->resregs));
-	if (host->cmd_va)
-		iounmap(host->cmd_va);
-	if (host->rescmd)
-		release_mem_region(host->rescmd->start,
-				resource_size(host->rescmd));
-	if (host->addr_va)
-		iounmap(host->addr_va);
-	if (host->resaddr)
-		release_mem_region(host->resaddr->start,
-				resource_size(host->resaddr));
-	if (host->data_va)
-		iounmap(host->data_va);
-	if (host->resdata)
-		release_mem_region(host->resdata->start,
-				resource_size(host->resdata));
-
-	kfree(host);
+err_clk_enable:
+	clk_put(host->clk);
 	return ret;
 }
 
@@ -1168,22 +1134,8 @@ static int fsmc_nand_remove(struct platform_device *pdev)
 		nand_release(&host->mtd);
 		clk_disable(host->clk);
 		clk_put(host->clk);
-
-		iounmap(host->regs_va);
-		release_mem_region(host->resregs->start,
-				resource_size(host->resregs));
-		iounmap(host->cmd_va);
-		release_mem_region(host->rescmd->start,
-				resource_size(host->rescmd));
-		iounmap(host->addr_va);
-		release_mem_region(host->resaddr->start,
-				resource_size(host->resaddr));
-		iounmap(host->data_va);
-		release_mem_region(host->resdata->start,
-				resource_size(host->resdata));
-
-		kfree(host);
 	}
+
 	return 0;
 }
 
-- 
1.7.0.4

[PATCH 16/18] fsmc/nand: Use dev_err to report error scenario

[Vipin Kumar]

fsmc controller takes time to calculate the bch8 codes and the error offsets.
The calculate logic checks for completion upto a timeout. This patch adds a
error print when this timer expires and the ecc or error offsets are not yet
calculated.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 08aa93e..1f00b37 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -464,6 +464,7 @@ struct fsmc_nand_data {
 
 	struct fsmc_eccplace	*ecc_place;
 	unsigned int		bank;
+	struct device		*dev;
 	struct clk		*clk;
 
 	struct fsmc_nand_timings *dev_timings;
@@ -625,6 +626,11 @@ static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
 			cond_resched();
 	} while (!time_after_eq(jiffies, deadline));
 
+	if (time_after_eq(jiffies, deadline)) {
+		dev_err(host->dev, "calculate ecc timed out\n");
+		return -ETIMEDOUT;
+	}
+
 	ecc_tmp = readl(&regs->bank_regs[bank].ecc1);
 	ecc[0] = (uint8_t) (ecc_tmp >> 0);
 	ecc[1] = (uint8_t) (ecc_tmp >> 8);
@@ -961,6 +967,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 
 	host->bank = pdata->bank;
 	host->select_chip = pdata->select_bank;
+	host->dev = &pdev->dev;
 	host->dev_timings = pdata->nand_timings;
 	regs = host->regs_va;
 
-- 
1.7.0.4

[PATCH 17/18] fsmc/nand: Access the NAND device word by word whenever possible

[Vipin Kumar]

The default way of accessing nand device is using the nand width. This means
that 8bit devices are using u8 * and 16bit devices are accessed using u16 *.

This results in a non-optimal performance since the FSMC is designed to
translate the normal word accesses into device width based accesses. This patch
implements read_buf and write_buf callbacks using word by word accesses.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |   55 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/fsmc.h     |    6 ++++
 2 files changed, 61 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 1f00b37..3828279 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -692,6 +692,52 @@ static int count_written_bits(uint8_t *buff, int size, int max_bits)
 }
 
 /*
+ * fsmc_write_buf - write buffer to chip
+ * @mtd:	MTD device structure
+ * @buf:	data buffer
+ * @len:	number of bytes to write
+ */
+static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+
+	if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
+			IS_ALIGNED(len, sizeof(uint32_t))) {
+		uint32_t *p = (uint32_t *)buf;
+		len = len >> 2;
+		for (i = 0; i < len; i++)
+			writel(p[i], chip->IO_ADDR_W);
+	} else {
+		for (i = 0; i < len; i++)
+			writeb(buf[i], chip->IO_ADDR_W);
+	}
+}
+
+/*
+ * fsmc_read_buf - read chip data into buffer
+ * @mtd:	MTD device structure
+ * @buf:	buffer to store date
+ * @len:	number of bytes to read
+ */
+static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+
+	if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
+			IS_ALIGNED(len, sizeof(uint32_t))) {
+		uint32_t *p = (uint32_t *)buf;
+		len = len >> 2;
+		for (i = 0; i < len; i++)
+			p[i] = readl(chip->IO_ADDR_R);
+	} else {
+		for (i = 0; i < len; i++)
+			buf[i] = readb(chip->IO_ADDR_R);
+	}
+}
+
+/*
  * fsmc_read_page_hwecc
  * @mtd:	mtd info structure
  * @chip:	nand chip info structure
@@ -993,6 +1039,15 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	if (pdata->width == FSMC_NAND_BW16)
 		nand->options |= NAND_BUSWIDTH_16;
 
+	/*
+	 * use customized (word by word) version of read_buf, write_buf if
+	 * access_with_dev_width is reset supported
+	 */
+	if (pdata->mode == USE_WORD_ACCESS) {
+		nand->read_buf = fsmc_read_buf;
+		nand->write_buf = fsmc_write_buf;
+	}
+
 	fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16,
 			host->dev_timings);
 
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h
index c4ac07a..1edd2b3 100644
--- a/include/linux/mtd/fsmc.h
+++ b/include/linux/mtd/fsmc.h
@@ -141,6 +141,11 @@ struct fsmc_nand_timings {
 	uint8_t tset;
 };
 
+enum access_mode {
+	USE_DMA_ACCESS = 1,
+	USE_WORD_ACCESS,
+};
+
 /**
  * fsmc_nand_platform_data - platform specific NAND controller config
  * @partitions: partition table for the platform, use a default fallback
@@ -164,6 +169,7 @@ struct fsmc_nand_platform_data {
 	/* CLE, ALE offsets */
 	unsigned long           cle_off;
 	unsigned long           ale_off;
+	enum access_mode	mode;
 
 	void			(*select_bank)(uint32_t bank, uint32_t busw);
 };
-- 
1.7.0.4

[PATCH 18/18] fsmc/nand: Add DMA support

[Vipin Kumar]

The fsmc_nand driver uses cpu to read/write onto the device. This is inefficient
because of two reasons
- the cpu gets locked on AHB bus while reading from NAND
- the cpu is unnecessarily used when dma can do the job

This patch adds the support for accessing the device through DMA

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |  173 ++++++++++++++++++++++++++++++++++++++++-
 include/linux/mtd/fsmc.h     |    4 +
 2 files changed, 172 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 3828279..5cc79bc 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -17,6 +17,10 @@
  */
 
 #include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-direction.h>
+#include <linux/dma-mapping.h>
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/module.h>
@@ -452,6 +456,11 @@ static struct mtd_partition partition_info_2048KB_blk[] = {
  * @bank:		Bank number for probed device.
  * @clk:		Clock structure for FSMC.
  *
+ * @read_dma_chan:	DMA channel for read access
+ * @write_dma_chan:	DMA channel for write access to NAND
+ * @dma_access_complete: Completion structure
+ *
+ * @data_pa:		NAND Physical port for Data.
  * @data_va:		NAND port for Data.
  * @cmd_va:		NAND port for Command.
  * @addr_va:		NAND port for Address.
@@ -465,10 +474,17 @@ struct fsmc_nand_data {
 	struct fsmc_eccplace	*ecc_place;
 	unsigned int		bank;
 	struct device		*dev;
+	enum access_mode	mode;
 	struct clk		*clk;
 
+	/* DMA related objects */
+	struct dma_chan		*read_dma_chan;
+	struct dma_chan		*write_dma_chan;
+	struct completion	dma_access_complete;
+
 	struct fsmc_nand_timings *dev_timings;
 
+	dma_addr_t		data_pa;
 	void __iomem		*data_va;
 	void __iomem		*cmd_va;
 	void __iomem		*addr_va;
@@ -691,6 +707,82 @@ static int count_written_bits(uint8_t *buff, int size, int max_bits)
 	return written_bits;
 }
 
+static void dma_complete(void *param)
+{
+	struct fsmc_nand_data *host = param;
+
+	complete(&host->dma_access_complete);
+}
+
+static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
+		enum dma_data_direction direction)
+{
+	struct dma_chan *chan;
+	struct dma_device *dma_dev;
+	struct dma_async_tx_descriptor *tx;
+	dma_addr_t dma_dst, dma_src, dma_addr;
+	dma_cookie_t cookie;
+	unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
+	int ret;
+
+	if (direction == DMA_TO_DEVICE)
+		chan = host->write_dma_chan;
+	else if (direction == DMA_FROM_DEVICE)
+		chan = host->read_dma_chan;
+	else
+		return -EINVAL;
+
+	dma_dev = chan->device;
+	dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
+
+	if (direction == DMA_TO_DEVICE) {
+		dma_src = dma_addr;
+		dma_dst = host->data_pa;
+		flags |= DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_SKIP_DEST_UNMAP;
+	} else {
+		dma_src = host->data_pa;
+		dma_dst = dma_addr;
+		flags |= DMA_COMPL_DEST_UNMAP_SINGLE | DMA_COMPL_SKIP_SRC_UNMAP;
+	}
+
+	tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
+			len, flags);
+
+	if (!tx) {
+		dev_err(host->dev, "device_prep_dma_memcpy error\n");
+		dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
+		return -EIO;
+	}
+
+	tx->callback = dma_complete;
+	tx->callback_param = host;
+	cookie = tx->tx_submit(tx);
+
+	ret = dma_submit_error(cookie);
+	if (ret) {
+		dev_err(host->dev, "dma_submit_error %d\n", cookie);
+		return ret;
+	}
+
+	dma_async_issue_pending(chan);
+
+	ret =
+	wait_for_completion_interruptible_timeout(&host->dma_access_complete,
+				msecs_to_jiffies(3000));
+	if (ret <= 0) {
+		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+		dev_err(host->dev, "wait_for_completion_timeout\n");
+		return ret ? ret : -ETIMEDOUT;
+	}
+
+	preempt_disable();
+	__this_cpu_add(chan->local->bytes_transferred, len);
+	__this_cpu_inc(chan->local->memcpy_count);
+	preempt_enable();
+
+	return 0;
+}
+
 /*
  * fsmc_write_buf - write buffer to chip
  * @mtd:	MTD device structure
@@ -738,6 +830,35 @@ static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 }
 
 /*
+ * fsmc_read_buf_dma - read chip data into buffer
+ * @mtd:	MTD device structure
+ * @buf:	buffer to store date
+ * @len:	number of bytes to read
+ */
+static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	struct fsmc_nand_data *host;
+
+	host = container_of(mtd, struct fsmc_nand_data, mtd);
+	dma_xfer(host, buf, len, DMA_FROM_DEVICE);
+}
+
+/*
+ * fsmc_write_buf_dma - write buffer to chip
+ * @mtd:	MTD device structure
+ * @buf:	data buffer
+ * @len:	number of bytes to write
+ */
+static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
+		int len)
+{
+	struct fsmc_nand_data *host;
+
+	host = container_of(mtd, struct fsmc_nand_data, mtd);
+	dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
+}
+
+/*
  * fsmc_read_page_hwecc
  * @mtd:	mtd info structure
  * @chip:	nand chip info structure
@@ -899,6 +1020,12 @@ static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	return i;
 }
 
+static bool filter(struct dma_chan *chan, void *slave)
+{
+	chan->private = slave;
+	return true;
+}
+
 /*
  * fsmc_nand_probe - Probe function
  * @pdev:       platform device structure
@@ -912,6 +1039,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	struct fsmc_regs *regs;
 	struct resource *res;
 	struct mtd_partition *parts;
+	dma_cap_mask_t mask;
 	int nr_parts;
 	int ret = 0;
 	u32 pid;
@@ -939,6 +1067,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 		return -ENOENT;
 	}
 
+	host->data_pa = (dma_addr_t)res->start;
 	host->data_va = devm_ioremap(&pdev->dev, res->start,
 			resource_size(res));
 	if (!host->data_va) {
@@ -1015,6 +1144,11 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	host->select_chip = pdata->select_bank;
 	host->dev = &pdev->dev;
 	host->dev_timings = pdata->nand_timings;
+	host->mode = pdata->mode;
+
+	if (host->mode == USE_DMA_ACCESS)
+		init_completion(&host->dma_access_complete);
+
 	regs = host->regs_va;
 
 	/* Link all private pointers */
@@ -1039,13 +1173,31 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	if (pdata->width == FSMC_NAND_BW16)
 		nand->options |= NAND_BUSWIDTH_16;
 
-	/*
-	 * use customized (word by word) version of read_buf, write_buf if
-	 * access_with_dev_width is reset supported
-	 */
-	if (pdata->mode == USE_WORD_ACCESS) {
+	switch (host->mode) {
+	case USE_DMA_ACCESS:
+		dma_cap_zero(mask);
+		dma_cap_set(DMA_MEMCPY, mask);
+		host->read_dma_chan = dma_request_channel(mask, filter,
+				pdata->read_dma_priv);
+		if (!host->read_dma_chan) {
+			dev_err(&pdev->dev, "Unable to get read dma channel\n");
+			goto err_req_read_chnl;
+		}
+		host->write_dma_chan = dma_request_channel(mask, filter,
+				pdata->write_dma_priv);
+		if (!host->write_dma_chan) {
+			dev_err(&pdev->dev, "Unable to get write dma channel\n");
+			goto err_req_write_chnl;
+		}
+		nand->read_buf = fsmc_read_buf_dma;
+		nand->write_buf = fsmc_write_buf_dma;
+		break;
+
+	default:
+	case USE_WORD_ACCESS:
 		nand->read_buf = fsmc_read_buf;
 		nand->write_buf = fsmc_write_buf;
+		break;
 	}
 
 	fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16,
@@ -1177,6 +1329,12 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 
 err_probe:
 err_scan_ident:
+	if (host->mode == USE_DMA_ACCESS)
+		dma_release_channel(host->write_dma_chan);
+err_req_write_chnl:
+	if (host->mode == USE_DMA_ACCESS)
+		dma_release_channel(host->read_dma_chan);
+err_req_read_chnl:
 	clk_disable(host->clk);
 err_clk_enable:
 	clk_put(host->clk);
@@ -1194,6 +1352,11 @@ static int fsmc_nand_remove(struct platform_device *pdev)
 
 	if (host) {
 		nand_release(&host->mtd);
+
+		if (host->mode == USE_DMA_ACCESS) {
+			dma_release_channel(host->write_dma_chan);
+			dma_release_channel(host->read_dma_chan);
+		}
 		clk_disable(host->clk);
 		clk_put(host->clk);
 	}
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h
index 1edd2b3..18f9127 100644
--- a/include/linux/mtd/fsmc.h
+++ b/include/linux/mtd/fsmc.h
@@ -172,6 +172,10 @@ struct fsmc_nand_platform_data {
 	enum access_mode	mode;
 
 	void			(*select_bank)(uint32_t bank, uint32_t busw);
+
+	/* priv structures for dma accesses */
+	void			*read_dma_priv;
+	void			*write_dma_priv;
 };
 
 extern int __init fsmc_nor_init(struct platform_device *pdev,
-- 
1.7.0.4

Re: [PATCH 18/18] fsmc/nand: Add DMA support

[Linus Walleij]

On Wed, Mar 7, 2012 at 12:31 PM, Vipin Kumar <vipin.kumar@st.com> wrote:

> The fsmc_nand driver uses cpu to read/write onto the device. This is inefficient
> because of two reasons
> - the cpu gets locked on AHB bus while reading from NAND
> - the cpu is unnecessarily used when dma can do the job
>
> This patch adds the support for accessing the device through DMA

Please elaborate a bit on how this is done, because I think it's new
stuff.

It appears that the FSMC is not like a slave device, i.e. not taking a
stream of bytes. Instead you use the memcpy() portions of the
dmaengine API to move data in/out of the flash pages to the
page currently handled by the controller.

Is this correct? I think it's pretty interesting since it's a new usecase
for in-kernel memcpy() which (AFAIK) has so far only been used
to accelerate network packet copying (correct me if wrong!).

Please add Dan Williams and Vinod Koul to CC on this patch so
the dmaengine people get to look at it.

Yours,
Linus Walleij

Re: [PATCH 18/18] fsmc/nand: Add DMA support

[Vipin Kumar]

On 3/7/2012 9:39 PM, Linus Walleij wrote:
> On Wed, Mar 7, 2012 at 12:31 PM, Vipin Kumar<vipin.kumar@st.com>  wrote:
>
>> The fsmc_nand driver uses cpu to read/write onto the device. This is inefficient
>> because of two reasons
>> - the cpu gets locked on AHB bus while reading from NAND
>> - the cpu is unnecessarily used when dma can do the job
>>
>> This patch adds the support for accessing the device through DMA
>
> Please elaborate a bit on how this is done, because I think it's new
> stuff.
>
> It appears that the FSMC is not like a slave device, i.e. not taking a
> stream of bytes. Instead you use the memcpy() portions of the
> dmaengine API to move data in/out of the flash pages to the
> page currently handled by the controller.
>

Yes, that's right. memcpy portions of dmaengine API are being used to 
move the data in/out of flash pages

> Is this correct? I think it's pretty interesting since it's a new usecase
> for in-kernel memcpy() which (AFAIK) has so far only been used
> to accelerate network packet copying (correct me if wrong!).
>

I also saw the same use case in drivers/ata/pata_arasan_cf.c. Have a 
look at dma_xfer routine in this file

Regards
Vipin

Re: [PATCH 18/18] fsmc/nand: Add DMA support

[Vipin Kumar]

Sending the patch to Vinod and Dan as suggested by linus
Regards
Vipin

On 3/7/2012 5:01 PM, Vipin KUMAR wrote:
> The fsmc_nand driver uses cpu to read/write onto the device. This is inefficient
> because of two reasons
> - the cpu gets locked on AHB bus while reading from NAND
> - the cpu is unnecessarily used when dma can do the job
>
> This patch adds the support for accessing the device through DMA
>
> Signed-off-by: Vipin Kumar<vipin.kumar@st.com>
> Reviewed-by: Viresh Kumar<viresh.kumar@st.com>
> ---
>   drivers/mtd/nand/fsmc_nand.c |  173 ++++++++++++++++++++++++++++++++++++++++-
>   include/linux/mtd/fsmc.h     |    4 +
>   2 files changed, 172 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
> index 3828279..5cc79bc 100644
> --- a/drivers/mtd/nand/fsmc_nand.c
> +++ b/drivers/mtd/nand/fsmc_nand.c
> @@ -17,6 +17,10 @@
>    */
>
>   #include<linux/clk.h>
> +#include<linux/completion.h>
> +#include<linux/dmaengine.h>
> +#include<linux/dma-direction.h>
> +#include<linux/dma-mapping.h>
>   #include<linux/err.h>
>   #include<linux/init.h>
>   #include<linux/module.h>
> @@ -452,6 +456,11 @@ static struct mtd_partition partition_info_2048KB_blk[] = {
>    * @bank:		Bank number for probed device.
>    * @clk:		Clock structure for FSMC.
>    *
> + * @read_dma_chan:	DMA channel for read access
> + * @write_dma_chan:	DMA channel for write access to NAND
> + * @dma_access_complete: Completion structure
> + *
> + * @data_pa:		NAND Physical port for Data.
>    * @data_va:		NAND port for Data.
>    * @cmd_va:		NAND port for Command.
>    * @addr_va:		NAND port for Address.
> @@ -465,10 +474,17 @@ struct fsmc_nand_data {
>   	struct fsmc_eccplace	*ecc_place;
>   	unsigned int		bank;
>   	struct device		*dev;
> +	enum access_mode	mode;
>   	struct clk		*clk;
>
> +	/* DMA related objects */
> +	struct dma_chan		*read_dma_chan;
> +	struct dma_chan		*write_dma_chan;
> +	struct completion	dma_access_complete;
> +
>   	struct fsmc_nand_timings *dev_timings;
>
> +	dma_addr_t		data_pa;
>   	void __iomem		*data_va;
>   	void __iomem		*cmd_va;
>   	void __iomem		*addr_va;
> @@ -691,6 +707,82 @@ static int count_written_bits(uint8_t *buff, int size, int max_bits)
>   	return written_bits;
>   }
>
> +static void dma_complete(void *param)
> +{
> +	struct fsmc_nand_data *host = param;
> +
> +	complete(&host->dma_access_complete);
> +}
> +
> +static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
> +		enum dma_data_direction direction)
> +{
> +	struct dma_chan *chan;
> +	struct dma_device *dma_dev;
> +	struct dma_async_tx_descriptor *tx;
> +	dma_addr_t dma_dst, dma_src, dma_addr;
> +	dma_cookie_t cookie;
> +	unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
> +	int ret;
> +
> +	if (direction == DMA_TO_DEVICE)
> +		chan = host->write_dma_chan;
> +	else if (direction == DMA_FROM_DEVICE)
> +		chan = host->read_dma_chan;
> +	else
> +		return -EINVAL;
> +
> +	dma_dev = chan->device;
> +	dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
> +
> +	if (direction == DMA_TO_DEVICE) {
> +		dma_src = dma_addr;
> +		dma_dst = host->data_pa;
> +		flags |= DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_SKIP_DEST_UNMAP;
> +	} else {
> +		dma_src = host->data_pa;
> +		dma_dst = dma_addr;
> +		flags |= DMA_COMPL_DEST_UNMAP_SINGLE | DMA_COMPL_SKIP_SRC_UNMAP;
> +	}
> +
> +	tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
> +			len, flags);
> +
> +	if (!tx) {
> +		dev_err(host->dev, "device_prep_dma_memcpy error\n");
> +		dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
> +		return -EIO;
> +	}
> +
> +	tx->callback = dma_complete;
> +	tx->callback_param = host;
> +	cookie = tx->tx_submit(tx);
> +
> +	ret = dma_submit_error(cookie);
> +	if (ret) {
> +		dev_err(host->dev, "dma_submit_error %d\n", cookie);
> +		return ret;
> +	}
> +
> +	dma_async_issue_pending(chan);
> +
> +	ret =
> +	wait_for_completion_interruptible_timeout(&host->dma_access_complete,
> +				msecs_to_jiffies(3000));
> +	if (ret<= 0) {
> +		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
> +		dev_err(host->dev, "wait_for_completion_timeout\n");
> +		return ret ? ret : -ETIMEDOUT;
> +	}
> +
> +	preempt_disable();
> +	__this_cpu_add(chan->local->bytes_transferred, len);
> +	__this_cpu_inc(chan->local->memcpy_count);
> +	preempt_enable();
> +
> +	return 0;
> +}
> +
>   /*
>    * fsmc_write_buf - write buffer to chip
>    * @mtd:	MTD device structure
> @@ -738,6 +830,35 @@ static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>   }
>
>   /*
> + * fsmc_read_buf_dma - read chip data into buffer
> + * @mtd:	MTD device structure
> + * @buf:	buffer to store date
> + * @len:	number of bytes to read
> + */
> +static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
> +{
> +	struct fsmc_nand_data *host;
> +
> +	host = container_of(mtd, struct fsmc_nand_data, mtd);
> +	dma_xfer(host, buf, len, DMA_FROM_DEVICE);
> +}
> +
> +/*
> + * fsmc_write_buf_dma - write buffer to chip
> + * @mtd:	MTD device structure
> + * @buf:	data buffer
> + * @len:	number of bytes to write
> + */
> +static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
> +		int len)
> +{
> +	struct fsmc_nand_data *host;
> +
> +	host = container_of(mtd, struct fsmc_nand_data, mtd);
> +	dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
> +}
> +
> +/*
>    * fsmc_read_page_hwecc
>    * @mtd:	mtd info structure
>    * @chip:	nand chip info structure
> @@ -899,6 +1020,12 @@ static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
>   	return i;
>   }
>
> +static bool filter(struct dma_chan *chan, void *slave)
> +{
> +	chan->private = slave;
> +	return true;
> +}
> +
>   /*
>    * fsmc_nand_probe - Probe function
>    * @pdev:       platform device structure
> @@ -912,6 +1039,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>   	struct fsmc_regs *regs;
>   	struct resource *res;
>   	struct mtd_partition *parts;
> +	dma_cap_mask_t mask;
>   	int nr_parts;
>   	int ret = 0;
>   	u32 pid;
> @@ -939,6 +1067,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>   		return -ENOENT;
>   	}
>
> +	host->data_pa = (dma_addr_t)res->start;
>   	host->data_va = devm_ioremap(&pdev->dev, res->start,
>   			resource_size(res));
>   	if (!host->data_va) {
> @@ -1015,6 +1144,11 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>   	host->select_chip = pdata->select_bank;
>   	host->dev =&pdev->dev;
>   	host->dev_timings = pdata->nand_timings;
> +	host->mode = pdata->mode;
> +
> +	if (host->mode == USE_DMA_ACCESS)
> +		init_completion(&host->dma_access_complete);
> +
>   	regs = host->regs_va;
>
>   	/* Link all private pointers */
> @@ -1039,13 +1173,31 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>   	if (pdata->width == FSMC_NAND_BW16)
>   		nand->options |= NAND_BUSWIDTH_16;
>
> -	/*
> -	 * use customized (word by word) version of read_buf, write_buf if
> -	 * access_with_dev_width is reset supported
> -	 */
> -	if (pdata->mode == USE_WORD_ACCESS) {
> +	switch (host->mode) {
> +	case USE_DMA_ACCESS:
> +		dma_cap_zero(mask);
> +		dma_cap_set(DMA_MEMCPY, mask);
> +		host->read_dma_chan = dma_request_channel(mask, filter,
> +				pdata->read_dma_priv);
> +		if (!host->read_dma_chan) {
> +			dev_err(&pdev->dev, "Unable to get read dma channel\n");
> +			goto err_req_read_chnl;
> +		}
> +		host->write_dma_chan = dma_request_channel(mask, filter,
> +				pdata->write_dma_priv);
> +		if (!host->write_dma_chan) {
> +			dev_err(&pdev->dev, "Unable to get write dma channel\n");
> +			goto err_req_write_chnl;
> +		}
> +		nand->read_buf = fsmc_read_buf_dma;
> +		nand->write_buf = fsmc_write_buf_dma;
> +		break;
> +
> +	default:
> +	case USE_WORD_ACCESS:
>   		nand->read_buf = fsmc_read_buf;
>   		nand->write_buf = fsmc_write_buf;
> +		break;
>   	}
>
>   	fsmc_nand_setup(regs, host->bank, nand->options&  NAND_BUSWIDTH_16,
> @@ -1177,6 +1329,12 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>
>   err_probe:
>   err_scan_ident:
> +	if (host->mode == USE_DMA_ACCESS)
> +		dma_release_channel(host->write_dma_chan);
> +err_req_write_chnl:
> +	if (host->mode == USE_DMA_ACCESS)
> +		dma_release_channel(host->read_dma_chan);
> +err_req_read_chnl:
>   	clk_disable(host->clk);
>   err_clk_enable:
>   	clk_put(host->clk);
> @@ -1194,6 +1352,11 @@ static int fsmc_nand_remove(struct platform_device *pdev)
>
>   	if (host) {
>   		nand_release(&host->mtd);
> +
> +		if (host->mode == USE_DMA_ACCESS) {
> +			dma_release_channel(host->write_dma_chan);
> +			dma_release_channel(host->read_dma_chan);
> +		}
>   		clk_disable(host->clk);
>   		clk_put(host->clk);
>   	}
> diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h
> index 1edd2b3..18f9127 100644
> --- a/include/linux/mtd/fsmc.h
> +++ b/include/linux/mtd/fsmc.h
> @@ -172,6 +172,10 @@ struct fsmc_nand_platform_data {
>   	enum access_mode	mode;
>
>   	void			(*select_bank)(uint32_t bank, uint32_t busw);
> +
> +	/* priv structures for dma accesses */
> +	void			*read_dma_priv;
> +	void			*write_dma_priv;
>   };
>
>   extern int __init fsmc_nor_init(struct platform_device *pdev,

Re: [PATCH 00/18] mtd/nand/fsmc related modifications

[Vipin Kumar]

Hello All,

It seems that Artem's mail id is an old one..Please remove it while 
replying to avoid getting bounces. The getmaintainer script needs to be 
updated with the correct mail id.

Regards
Vipin

On 3/7/2012 5:00 PM, Vipin KUMAR wrote:
> Hello All,
>
> Please find the nand/fsmc driver modifications
> Major modifications include
> - DMA support
> - Word read/write support to improve performance
> - Move platform related things(ALE/CLE) from driver to platfrom files
> - Add default partition support for more devices with erase sizes (256KB, 512KB,
> 		1024KB, 2048KB)
> - Bugfixes
> 	- Read only 512 + 13 bytes for 8bit NAND devices
> 	- Flip the bit only if the error index is<  4096
> 	- Fixed data abort inside change_bit()
>
> Armando Visconti (4):
>    fsmc_nand.c: Fixed data abort inside change_bit()
>    nand/fsmc: Improve the fsmc_correct_data() routine
>    fsmc_nand.c: Support of 224-bytes OOB area length
>    fsmc/nand: Add support for default partitions for several NAND
>      devices
>
> Bhavna Yadav (1):
>    mtd/fsmc_nand: ECC1&  ECC4 layout separated for different page sizes
>
> Shiraz Hashim (3):
>    nand/fsmc: use ALE and CLE offsets from platform data
>    mtd/nand/fsmc: Move ALE, CLE defines to their respective platform
>    mtd/fsmc_nand: add pm callbacks to support hibernation
>
> Vipin Kumar (10):
>    nand/fsmc: Newly erased page read algorithm implemented
>    nand/fsmc: Correct the multiline comment format
>    nand/fsmc: Read only 512 + 13 bytes for 8bit NAND devices
>    nand/fsmc: Flip the bit only if the error index is<  4096
>    nand/fsmc: Initialize the badblockbits to 7
>    fsmc/nand: Modify fsmc driver to accept nand timing parameters via
>      platform
>    fsmc/nand: Use devm routines
>    fsmc/nand: Use dev_err to report error scenario
>    fsmc/nand: Access the NAND device word by word whenever possible
>    fsmc/nand: Add DMA support
>
>   arch/arm/mach-u300/core.c                   |    2 +
>   arch/arm/mach-u300/include/mach/u300-regs.h |    5 +
>   drivers/mtd/nand/fsmc_nand.c                |  900 ++++++++++++++++++++++-----
>   include/linux/mtd/fsmc.h                    |   62 ++-
>   4 files changed, 788 insertions(+), 181 deletions(-)
>
> .
>

Re: [PATCH 00/18] mtd/nand/fsmc related modifications

[Artem Bityutskiy]

On Wed, 2012-03-07 at 17:00 +0530, Vipin Kumar wrote:
> Hello All,

BTW, sparse gives a lot of warnings like this for this driver:

drivers/mtd/nand/fsmc_nand.c:300:9: warning: incorrect type in argument 1 (different address spaces) [sparse]
drivers/mtd/nand/fsmc_nand.c:300:9:    expected void const volatile [noderef] <asn:2>*<noident> [sparse]
drivers/mtd/nand/fsmc_nand.c:300:9:    got unsigned int *<noident> [sparse]

-- 
Best Regards,
Artem Bityutskiy

Re: [PATCH 00/18] mtd/nand/fsmc related modifications

[Artem Bityutskiy]

On Wed, 2012-03-07 at 17:00 +0530, Vipin Kumar wrote:
> Hello All,
> 
> Please find the nand/fsmc driver modifications
> Major modifications include
> - DMA support
> - Word read/write support to improve performance
> - Move platform related things(ALE/CLE) from driver to platfrom files
> - Add default partition support for more devices with erase sizes (256KB, 512KB,
> 		1024KB, 2048KB)
> - Bugfixes
> 	- Read only 512 + 13 bytes for 8bit NAND devices
> 	- Flip the bit only if the error index is < 4096
> 	- Fixed data abort inside change_bit()

Pushed patches 1-7 to l2-mtd.git. Patch 8 look wrong to me, the other
won't apply without patch 8 so I did not look beyond patch 7. Thanks!

But please, confirm that it is OK to have only some of these patches
merged, not the complete set. Thanks!

-- 
Best Regards,
Artem Bityutskiy

Re: [PATCH 00/18] mtd/nand/fsmc related modifications

[Vipin Kumar]

On 3/9/2012 6:56 PM, Artem Bityutskiy wrote:
> On Wed, 2012-03-07 at 17:00 +0530, Vipin Kumar wrote:
>> Hello All,
>>
>> Please find the nand/fsmc driver modifications
>> Major modifications include
>> - DMA support
>> - Word read/write support to improve performance
>> - Move platform related things(ALE/CLE) from driver to platfrom files
>> - Add default partition support for more devices with erase sizes (256KB, 512KB,
>> 		1024KB, 2048KB)
>> - Bugfixes
>> 	- Read only 512 + 13 bytes for 8bit NAND devices
>> 	- Flip the bit only if the error index is<  4096
>> 	- Fixed data abort inside change_bit()
>
> Pushed patches 1-7 to l2-mtd.git. Patch 8 look wrong to me, the other
> won't apply without patch 8 so I did not look beyond patch 7. Thanks!
>
> But please, confirm that it is OK to have only some of these patches
> merged, not the complete set. Thanks!
>

Please find the patch-set v2 in another mail. This patch-set contains 
only the remaining patches from the original patch-set

Regards
Vipin