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Wed, 30 Sep 2020 16:04:00 +0300 (MSK) Received: from T-EXCH-04.corp.yadro.com (t-exch-04.corp.yadro.com [172.17.100.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mta-01.yadro.com (Postfix) with ESMTPS id C084041207; Wed, 30 Sep 2020 16:04:00 +0300 (MSK) Received: from localhost.localdomain (10.199.2.122) by T-EXCH-04.corp.yadro.com (172.17.100.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.669.32; Wed, 30 Sep 2020 16:04:00 +0300 Message-ID: <4a5945534f7b41cb799c044ec8c9d31c61d5beda.camel@yadro.com> Subject: Re: [RESEND PATCH 1/2] mtd: spi-nor: do not touch TB bit without SPI_NOR_HAS_TB From: Ivan Mikhaylov To: Vignesh Raghavendra , Tudor Ambarus , Miquel Raynal , Richard Weinberger Date: Wed, 30 Sep 2020 16:07:53 +0300 In-Reply-To: <9bfb10df-64d8-4a5e-b0ad-a8b5f4efc56f@ti.com> References: <20200921112450.4824-1-i.mikhaylov@yadro.com> <20200921112450.4824-2-i.mikhaylov@yadro.com> <9bfb10df-64d8-4a5e-b0ad-a8b5f4efc56f@ti.com> Organization: YADRO User-Agent: Evolution 3.32.5 (3.32.5-1.fc30) MIME-Version: 1.0 X-Originating-IP: [10.199.2.122] X-ClientProxiedBy: T-EXCH-01.corp.yadro.com (172.17.10.101) To T-EXCH-04.corp.yadro.com (172.17.100.104) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200930_090406_632736_9143A97B X-CRM114-Status: GOOD ( 14.88 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On Wed, 2020-09-30 at 15:06 +0530, Vignesh Raghavendra wrote: > > On 9/21/20 4:54 PM, Ivan Mikhaylov wrote: > > Some chips like macronix don't have TB(Top/Bottom protection) > > bit in the status register. Do not write tb_mask inside status > > register, unless SPI_NOR_HAS_TB is present for the chip. > > > > Not entirely accurate.. Macronix chips have TB bit in config register > and is OTP and hence should not be touched ideally... > > You still need to "read" that bit to determine actual scheme (Top vs > Bottom). This is needs to be done before 2/2 enables SPI_NOR_HAS_LOCK > flag for macronix flashes. Vignesh, that's the point about this commit to generalize this part about TB bit plus there is already exist SPI_NOR_HAS_TB flag which representing state of TB existence. I didn't add any support for macronix's TB bit, that's true but that's enough to make macronix chips able to use lock mechanism with default 'use_top' or any other chips which doesn't have TB bit. > I guess macronix does not support SR_SRWD right? This needs special > treatment as well. It does support SR_SRWD as well. No need any special treatment here. Thanks. ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/