From: Tudor Ambarus <tudor.ambarus@linaro.org>
To: Fabio Estevam <festevam@gmail.com>, Michael Walle <michael@walle.cc>
Cc: pratyush@kernel.org, miquel.raynal@bootlin.com, richard@nod.at,
vigneshr@ti.com, linux-mtd@lists.infradead.org,
Fabio Estevam <festevam@denx.de>,
tkuw584924@gmail.com
Subject: Re: [PATCH] mtd: spi-nor: micron-st: Add support for mt25qu01g
Date: Tue, 24 Oct 2023 16:53:37 +0100 [thread overview]
Message-ID: <4faa5d37-ddf8-4edd-bb0e-a192d16df488@linaro.org> (raw)
In-Reply-To: <CAOMZO5BfEsB2vv__F7kkMo9Q-oHD5PiCmaK-ruU-ds9XabUc4Q@mail.gmail.com>
On 10/24/23 16:47, Fabio Estevam wrote:
> Hi Michael,
>
> On Tue, Oct 24, 2023 at 10:59 AM Michael Walle <michael@walle.cc> wrote:
>
>> You'd need to change the core to assume there is no chip
>> erase support if "n_dice > 1". So first step would be that
>> your SPI flash will successfully parse the SFDP and set n_dice
>> correctly. Then adapt the core to set SNOR_F_NO_OP_CHIP_ERASE
>> if "n_dice > 1".
>> The goal here is to avoid any entry in our database at all and
>> support this flash out of the box by just parsing SFDP correctly.
>
> Where in SFDP is located the information about the number of dies?
drivers/mtd/spi-nor/sfdp.c, search for n_dice. spi_nor_parse_sccr_mc()
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next prev parent reply other threads:[~2023-10-24 15:53 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 21:38 [PATCH] mtd: spi-nor: micron-st: Add support for mt25qu01g Fabio Estevam
2023-10-24 6:01 ` Tudor Ambarus
2023-10-24 13:57 ` Fabio Estevam
2023-10-24 14:23 ` Tudor Ambarus
2023-10-24 9:26 ` Michael Walle
2023-10-24 11:43 ` Fabio Estevam
2023-10-24 13:59 ` Michael Walle
2023-10-24 15:47 ` Fabio Estevam
2023-10-24 15:53 ` Tudor Ambarus [this message]
2023-10-24 16:20 ` Fabio Estevam
2023-10-24 16:36 ` Michael Walle
2023-10-24 16:43 ` Fabio Estevam
2023-10-25 3:34 ` Tudor Ambarus
2023-10-25 11:56 ` Fabio Estevam
2023-10-25 17:35 ` Fabio Estevam
2023-10-26 6:33 ` Michael Walle
2023-10-26 11:25 ` Fabio Estevam
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