From: Matthieu CASTET <matthieu.castet@parrot.com>
To: Scott Wood <scottwood@freescale.com>
Cc: Marek Vasut <marex@denx.de>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
David Woodhouse <dwmw2@infradead.org>,
Artem Bityutskiy <dedekind1@gmail.com>
Subject: Re: [PATCH RESEND] mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver
Date: Wed, 1 Aug 2012 15:05:04 +0200 [thread overview]
Message-ID: <50192980.7050303@parrot.com> (raw)
In-Reply-To: <501803C5.8080105@freescale.com>
Hi Scott,
Scott Wood a écrit :
> On 07/31/2012 02:33 AM, Matthieu CASTET wrote:
>> Hi,
>>
>> for ONFI flash (like this micron one) the information should be extracted form
>> the ONFI table (programs_per_page IIRC)
>>
>> This should be better than relying on the SOC driver for setting this flags.
>
> This is for cases where the constraint is the controller, not the chip.
>
>> Does the gpmi driver set this flag because it do not support partial write ?
>> In this case why it doesn't set chip->ecc.steps to 1 ?
>
> Why is it better to lie about ECC geometry than to just say "subpage
> writes aren't supported"? Does/will the ECC geometry get used by upper
> layers in evaluating the number of corrected bitflips?
If it is not because of ecc geometry, why the controller doesn't support subpage
writes ?
Matthieu
next prev parent reply other threads:[~2012-08-01 13:05 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-31 1:02 [PATCH RESEND] mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver Brian Norris
2012-07-31 4:17 ` Marek Vasut
2012-07-31 7:33 ` Matthieu CASTET
2012-07-31 13:20 ` Marek Vasut
2012-07-31 13:28 ` Matthieu CASTET
2012-07-31 13:59 ` Marek Vasut
2012-07-31 14:09 ` Matthieu CASTET
2012-07-31 14:12 ` Marek Vasut
2012-07-31 16:11 ` Scott Wood
2012-08-01 2:21 ` Huang Shijie
2012-08-01 13:05 ` Matthieu CASTET [this message]
2012-08-01 16:15 ` Scott Wood
2012-08-02 1:08 ` Brian Norris
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