Re: [PATCH] driver/mtd/ifc: Read Status while programming NAND flash

[Prabhakar Kushwaha <prabhakar@freescale.com>]

Hi Artem,

This patch is present in upstream review list from a long time.
There are no review comments.

So, I request you to pick this patch for linux-mtd.git repository.

Regards,
Prabhakar


On 10/03/2013 11:36 AM, Prabhakar Kushwaha wrote:
> as per controller description,
>    "While programming a NAND flash, status read should never skipped.
>     Because it may happen that a new command is issued to the NAND Flash,
>     even when the device has not yet finished processing the previous request.
>     This may result in unpredictable behaviour."
>
> IFC controller never polls for R/B signal after command send. It just return
> control to software. This behaviour may not occur with NAND flash access.
> because new commands are sent after polling R/B signal. But it may happen
> in scenario where GPCM-ASIC and NAND flash device are working simultaneously.
>
> Update the controller driver to take care of this requirement
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
>   drivers/mtd/nand/fsl_ifc_nand.c |   34 ++++++++++++++++++++++++----------
>   1 file changed, 24 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
> index a14885b..eb150f1 100644
> --- a/drivers/mtd/nand/fsl_ifc_nand.c
> +++ b/drivers/mtd/nand/fsl_ifc_nand.c
> @@ -504,20 +504,29 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
>   		if (mtd->writesize > 512) {
>   			nand_fcr0 =
>   				(NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
> -				(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
> +				(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
> +				(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
>   
>   			iowrite32be(
> -				(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> -				(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
> -				(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
> -				(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
> -				(IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT),
> -				&ifc->ifc_nand.nand_fir0);
> +				 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> +				 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
> +				 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
> +				 (IFC_FIR_OP_WBCD  << IFC_NAND_FIR0_OP3_SHIFT) |
> +				 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
> +				 &ifc->ifc_nand.nand_fir0);
> +			iowrite32be(
> +				 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
> +				 (IFC_FIR_OP_RDSTAT <<
> +					IFC_NAND_FIR1_OP6_SHIFT) |
> +				 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
> +				 &ifc->ifc_nand.nand_fir1);
>   		} else {
>   			nand_fcr0 = ((NAND_CMD_PAGEPROG <<
>   					IFC_NAND_FCR0_CMD1_SHIFT) |
>   				    (NAND_CMD_SEQIN <<
> -					IFC_NAND_FCR0_CMD2_SHIFT));
> +					IFC_NAND_FCR0_CMD2_SHIFT) |
> +				    (NAND_CMD_STATUS <<
> +					IFC_NAND_FCR0_CMD3_SHIFT));
>   
>   			iowrite32be(
>   				(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> @@ -526,8 +535,13 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
>   				(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
>   				(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
>   				&ifc->ifc_nand.nand_fir0);
> -			iowrite32be(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT,
> -				    &ifc->ifc_nand.nand_fir1);
> +			iowrite32be(
> +				 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
> +				 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
> +				 (IFC_FIR_OP_RDSTAT <<
> +					IFC_NAND_FIR1_OP7_SHIFT) |
> +				 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
> +				  &ifc->ifc_nand.nand_fir1);
>   
>   			if (column >= mtd->writesize)
>   				nand_fcr0 |=