From: Sourav Poddar <sourav.poddar@ti.com>
To: Marek Vasut <marex@denx.de>
Cc: computersforpeace@gmail.com, linux-mtd@lists.infradead.org,
balbi@ti.com, dedekind1@gmail.com
Subject: Re: [PATCH] drivers: mtd: m25p80: Add quad read support.
Date: Mon, 28 Oct 2013 00:07:39 +0530 [thread overview]
Message-ID: <526D5D73.9060104@ti.com> (raw)
In-Reply-To: <201310271930.34528.marex@denx.de>
Dear Marek,
On Monday 28 October 2013 12:00 AM, Marek Vasut wrote:
> Dear Sourav Poddar,
>
>> Dear Marek,
>>
>> On Sunday 27 October 2013 10:15 PM, Marek Vasut wrote:
>>> Dear Sourav Poddar,
>>>
>>> [...]
> [...]
>
>>>> @@ -774,7 +906,7 @@ static const struct spi_device_id m25p_ids[] = {
>>>>
>>>> { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
>>>> { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
>>>> { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
>>>>
>>>> - { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) },
>>>> + { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, M25P80_QUAD_READ)
>>>> },
>>> I'm not convinced enabling 4-bit mode should be hard-coded in the MTD
>>> driver. There might be a board which uses this chip in 1-bit mode.
>>>
>>> We have a setup with Spansion chip here which uses 1-bit addressing in
>>> U-Boot, but uses 4-bit addressing in Linux. We use a DT property to
>>> configure the SPI bus width for that and I think that's a way to go.
>>> Note that there also are chips which use 2-bit wide SPI communication.
>> Yes, but if you trace down the patch below, you will see its not hard
>> coded. Enabling quad read mode depends on the following:
>>
>> 1. Whether flash chip supports it.
>> This information comes from the flash which we are setting above.
>>
>> 2. Whether SPI controller supports it.
>> This information is the check down below in the
>> patch(spi->mode& SPI_RX_QUAD).
>> spi->mode is set to "SINGLE/DUAL/QUAD" in the SPI framework
>> based on the
>> dt property "spi-tx/rx-bus-width".
>> So, unless you set spi->mode to SPI_RX_QUAD by setting
>> "spi-rx-bus-width" to 4 in dt, default
>> will be 1 bit mode only.
> So this M25P80_QUAD_READ flag tells us "this chip supports quad read", not
> "force enable quad read" .
Yes, correct.
> All right, thanks for clearing this up. I hope it's
> documented somewhere elsewhere than in this email ;-)
Its added as a comment under struct flash_info where
this flag is defined.
> Best regards,
> Marek Vasut
next prev parent reply other threads:[~2013-10-27 18:38 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-25 9:25 [PATCH] drivers: mtd: m25p80: Add quad read support Sourav Poddar
2013-10-25 10:18 ` Huang Shijie
2013-10-25 10:19 ` Sourav Poddar
2013-10-27 16:45 ` Marek Vasut
2013-10-27 18:26 ` Sourav Poddar
2013-10-27 18:30 ` Marek Vasut
2013-10-27 18:37 ` Sourav Poddar [this message]
2013-10-27 18:47 ` Marek Vasut
2013-10-29 5:57 ` Sourav Poddar
2013-10-29 14:01 ` Marek Vasut
2013-10-29 14:08 ` Sourav Poddar
2013-10-29 15:27 ` Marek Vasut
2013-10-29 16:52 ` Sourav Poddar
2013-10-29 17:08 ` Marek Vasut
2013-10-29 17:12 ` Sourav Poddar
2013-10-29 18:24 ` Marek Vasut
2013-10-29 18:34 ` Sourav Poddar
2013-10-30 6:27 ` Huang Shijie
2013-10-30 6:46 ` Sourav Poddar
2013-10-30 6:54 ` Huang Shijie
2013-10-30 10:11 ` Marek Vasut
2013-11-12 18:13 ` Brian Norris
-- strict thread matches above, loose matches on Subject: below --
2013-09-24 12:10 Sourav Poddar
2013-09-25 3:06 ` Huang Shijie
2013-09-25 5:20 ` Sourav Poddar
2013-09-25 5:48 ` Huang Shijie
2013-09-25 5:51 ` Sourav Poddar
2013-09-25 5:54 ` Sourav Poddar
2013-09-25 5:56 ` Huang Shijie
2013-09-25 6:16 ` Huang Shijie
2013-09-25 6:24 ` Sourav Poddar
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