From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from arroyo.ext.ti.com ([192.94.94.40]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VaVE0-0003by-Vj for linux-mtd@lists.infradead.org; Sun, 27 Oct 2013 18:38:09 +0000 Message-ID: <526D5D73.9060104@ti.com> Date: Mon, 28 Oct 2013 00:07:39 +0530 From: Sourav Poddar MIME-Version: 1.0 To: Marek Vasut Subject: Re: [PATCH] drivers: mtd: m25p80: Add quad read support. References: <1382693145-15750-1-git-send-email-sourav.poddar@ti.com> <201310271745.17152.marex@denx.de> <526D5AC8.2020703@ti.com> <201310271930.34528.marex@denx.de> In-Reply-To: <201310271930.34528.marex@denx.de> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Cc: computersforpeace@gmail.com, linux-mtd@lists.infradead.org, balbi@ti.com, dedekind1@gmail.com List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Dear Marek, On Monday 28 October 2013 12:00 AM, Marek Vasut wrote: > Dear Sourav Poddar, > >> Dear Marek, >> >> On Sunday 27 October 2013 10:15 PM, Marek Vasut wrote: >>> Dear Sourav Poddar, >>> >>> [...] > [...] > >>>> @@ -774,7 +906,7 @@ static const struct spi_device_id m25p_ids[] = { >>>> >>>> { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, >>>> { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, >>>> { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, >>>> >>>> - { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) }, >>>> + { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, M25P80_QUAD_READ) >>>> }, >>> I'm not convinced enabling 4-bit mode should be hard-coded in the MTD >>> driver. There might be a board which uses this chip in 1-bit mode. >>> >>> We have a setup with Spansion chip here which uses 1-bit addressing in >>> U-Boot, but uses 4-bit addressing in Linux. We use a DT property to >>> configure the SPI bus width for that and I think that's a way to go. >>> Note that there also are chips which use 2-bit wide SPI communication. >> Yes, but if you trace down the patch below, you will see its not hard >> coded. Enabling quad read mode depends on the following: >> >> 1. Whether flash chip supports it. >> This information comes from the flash which we are setting above. >> >> 2. Whether SPI controller supports it. >> This information is the check down below in the >> patch(spi->mode& SPI_RX_QUAD). >> spi->mode is set to "SINGLE/DUAL/QUAD" in the SPI framework >> based on the >> dt property "spi-tx/rx-bus-width". >> So, unless you set spi->mode to SPI_RX_QUAD by setting >> "spi-rx-bus-width" to 4 in dt, default >> will be 1 bit mode only. > So this M25P80_QUAD_READ flag tells us "this chip supports quad read", not > "force enable quad read" . Yes, correct. > All right, thanks for clearing this up. I hope it's > documented somewhere elsewhere than in this email ;-) Its added as a comment under struct flash_info where this flag is defined. > Best regards, > Marek Vasut