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From: Stefan Roese <sr@denx.de>
To: Brian Norris <computersforpeace@gmail.com>
Cc: linux-mtd@lists.infradead.org,
	Linus Walleij <linus.walleij@linaro.org>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	Boris Brezillon <boris.brezillon@free-electrons.com>
Subject: Re: [PATCH] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600
Date: Fri, 2 Oct 2015 12:33:58 +0200	[thread overview]
Message-ID: <560E5D96.5050208@denx.de> (raw)
In-Reply-To: <20150929002127.GP31505@google.com>

Hi Brian,

On 29.09.2015 02:21, Brian Norris wrote:
> On Wed, Sep 02, 2015 at 11:53:01AM +0200, Stefan Roese wrote:
>> This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
>> be used by boards equipped with a NAND chip that requires 4-bit ECC
>> strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.
>>
>> To enable SW BCH4, you need to specify this in your nand controller
>> DT node:
>>
>> 	nand-ecc-mode = "soft_bch";
>
> Please update the DT binding file, referring to nand.txt. Just specify
> your additional restrictions (like, should be "soft_bch" or "hw").
>
> Also please use nand-ecc-strength and nand-ecc-size; see below.

Thanks for the review. I'll send a new patch (series) out shortly,
addressing all your comments and suggestions.

Thanks,
Stefan

      reply	other threads:[~2015-10-02 10:34 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-02  9:53 [PATCH] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600 Stefan Roese
2015-09-02 11:12 ` Viresh Kumar
2015-09-29  0:21 ` Brian Norris
2015-10-02 10:33   ` Stefan Roese [this message]

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