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From: <Tudor.Ambarus@microchip.com>
To: <zhengxunli@mxic.com.tw>, <linux-mtd@lists.infradead.org>,
	<linux-spi@vger.kernel.org>
Cc: <p.yadav@ti.com>, <miquel.raynal@bootlin.com>,
	<broonie@kernel.org>, <jaimeliao@mxic.com.tw>
Subject: Re: [PATCH v5 1/2] mtd: spi-nor: macronix: add support for Macronix octaflash
Date: Tue, 29 Jun 2021 06:37:01 +0000	[thread overview]
Message-ID: <59855ba0-31d8-25b4-3000-ca493a83fe00@microchip.com> (raw)
In-Reply-To: <1621232088-12567-2-git-send-email-zhengxunli@mxic.com.tw>

On 5/17/21 9:14 AM, Zhengxun Li wrote:
> +       { "mx66lm1g45g", INFO(0xc2853b, 0, 32 * 1024, 4096,
> +                             SECT_4K | SPI_NOR_OCTAL_DTR_READ |
> +                             SPI_NOR_OCTAL_DTR_PP | SPI_NOR_4B_OPCODES)
> +               .fixups = &octaflash_fixups },

I have a mx66lm1g45g which does not define SFDP tables, how you'll differentiate
between the two? Mine will fail after reset. I'm working to address the flash ID
collisions, will send patches soon. I won't queue any new flash additions until
we'll solve the ID collisions problem.
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  parent reply	other threads:[~2021-06-29  6:38 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-17  6:14 [PATCH v5 0/2] Add octal DTR support for Macronix flash Zhengxun Li
2021-05-17  6:14 ` [PATCH v5 1/2] mtd: spi-nor: macronix: add support for Macronix octaflash Zhengxun Li
2021-05-17  7:33   ` Pratyush Yadav
2021-06-29  2:06     ` zhengxunli
2021-06-29  6:37   ` Tudor.Ambarus [this message]
2021-06-29  9:33     ` zhengxunli
2021-06-30  9:03     ` zhengxunli
2021-05-17  6:14 ` [PATCH v5 2/2] spi: mxic: patch for octal DTR mode support Zhengxun Li
2021-05-17 15:49   ` Mark Brown
2021-05-17 16:06   ` Pratyush Yadav
2021-05-18  2:47     ` zhengxunli

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