How does an SPI NOR handle a single byte write in Octal DTR mode?

How does an SPI NOR handle a single byte write in Octal DTR mode?

[Tudor.Ambarus]

Hello,

We're trying to understand how flashes handle single byte writes in
Octal DTR mode, and since we haven't found this info in the datasheets
that we read, you're our only hope. Can you shed some light and let us
now:
1/  Do the flashes ignore the second byte in Octal DTR mode? Are we forced
to first read the byte that we want to update together with the second byte,
so that when writing in Octal DTR mode to write the 2nd byte that we've just
read, so that we don't change its value?
2/ Can reads or writes start at an odd address in 8D-8D-8D mode? Pratyush
proposed something at:
https://patchwork.ozlabs.org/project/linux-mtd/list/?series=246518
Are the assumptions correct in the patch set?

Feel free to forward this to anyone interested. Thanks.
ta
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Re: How does an SPI NOR handle a single byte write in Octal DTR mode?

[Takahiro Kuwano]

Hi Tudor,

In case of Infineon(Cypress) S28 devices, it can be done by de-asserting
chip select before clock falling (not sure typical controllers support this).
That means the device can take odd address in 8D-8D-8D mode.

Thanks,
Takahiro

On 12/20/2021 6:36 PM, Tudor.Ambarus@microchip.com wrote:
> Hello,
> 
> We're trying to understand how flashes handle single byte writes in
> Octal DTR mode, and since we haven't found this info in the datasheets
> that we read, you're our only hope. Can you shed some light and let us
> now:
> 1/  Do the flashes ignore the second byte in Octal DTR mode? Are we forced
> to first read the byte that we want to update together with the second byte,
> so that when writing in Octal DTR mode to write the 2nd byte that we've just
> read, so that we don't change its value?
> 2/ Can reads or writes start at an odd address in 8D-8D-8D mode? Pratyush
> proposed something at:
> https://patchwork.ozlabs.org/project/linux-mtd/list/?series=246518
> Are the assumptions correct in the patch set?
> 
> Feel free to forward this to anyone interested. Thanks.
> ta
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 

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Re: How does an SPI NOR handle a single byte write in Octal DTR mode?

[Michael Walle]

Hi,

Am 2021-12-20 11:32, schrieb Takahiro Kuwano:
> In case of Infineon(Cypress) S28 devices, it can be done by 
> de-asserting
> chip select before clock falling (not sure typical controllers support 
> this).
> That means the device can take odd address in 8D-8D-8D mode.

Ahh nice. FWIW, I had a quick look at the FlexSPI controller found on
the NXP LS1028A, it doesn't seem to support deasserting the CS after
half a clock cycle, though.

-michael

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Re: How does an SPI NOR handle a single byte write in Octal DTR mode?

[Takahiro Kuwano]

Hi,

I need to correct my previous statement.

On 12/21/2021 12:47 AM, Michael Walle wrote:
> Hi,
> 
> Am 2021-12-20 11:32, schrieb Takahiro Kuwano:
>> In case of Infineon(Cypress) S28 devices, it can be done by de-asserting
>> chip select before clock falling (not sure typical controllers support this).
This is true for single-byte register write op.

>> That means the device can take odd address in 8D-8D-8D mode.
For page program op, the S28 in 8D-8D-8D mode only supports programming
multiples of 2-bytes and the address must start at an even address.

> 
> Ahh nice. FWIW, I had a quick look at the FlexSPI controller found on
> the NXP LS1028A, it doesn't seem to support deasserting the CS after
> half a clock cycle, though.
> 
> -michael

Thanks,
Takahiro

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