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From: Mok Keith <ek9852@gmail.com>
To: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: linux-mtd@lists.infradead.org, kyungmin.park@samsung.com,
	Eric Miao <eric.y.miao@gmail.com>,
	David Woodhouse <david.woodhouse@intel.com>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 1/5] pxa3xx_nand: enable PXA3xx bad block management
Date: Sat, 26 Sep 2009 01:04:47 +0800	[thread overview]
Message-ID: <69f617130909251004y2a17cdetb45f6022a37b4249@mail.gmail.com> (raw)
In-Reply-To: <771cded00909250457w19686a53obdc178488368dd43@mail.gmail.com>

Hi,

Any reason to limit the max slot to 40 (PXA_MAX_SLOT). It seems the
bad block management scheme is not scalable and have a limitation of
up to 256M bytes flash size only. (256M, 128kB per block = 2048 blocks
= 40 bad blocks)

Also for the calibration of the 2% bad block area, according to most
NAND specifications (checked Samsung, Hynix, Micron), nand flash
vendor guarantee no more than 20 bad block per 1024 blocks and this
rule is apply linearly.

Would it be better to use the following otherwise when nand size is
greater than 256M the no of bad block entries is not matched to
specification:
instead of:
> +    entries = (entries * 2) / 100;

use:
+    entries = (entries * 10) / 512;

May I know what is the use of PXA_BEGIN_SLOT ?

Keith

  reply	other threads:[~2009-09-25 17:04 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-09-25 11:57 [PATCH 1/5] pxa3xx_nand: enable PXA3xx bad block management Haojian Zhuang
2009-09-25 17:04 ` Mok Keith [this message]
2009-09-26  2:00   ` Haojian Zhuang
2009-10-08  3:12     ` Haojian Zhuang
2009-10-08 13:39       ` Eric Miao

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