Re: [PATCH v3] mtd: spi-nor: fix spansion quad enable

[Marek Vasut <marek.vasut@gmail.com>]

On 11/25/2016 03:50 PM, Cyrille Pitchen wrote:
> Hi Marek,

Hi,

> Le 25/11/2016 à 15:17, Marek Vasut a écrit :
>> On 11/23/2016 12:47 PM, Joël Esponde wrote:
>>> With the S25FL127S nor flash part, each writing to the configuration
>>> register takes hundreds of ms. During that  time, no more accesses to
>>> the flash should be done (even reads).
>>>
>>> This commit adds a wait loop after the register writing until the flash
>>> finishes its work.
>>>
>>> This issue could make rootfs mounting fail when the latter was done too
>>> much closely to this quad enable bit setting step. And in this case, a
>>> driver as UBIFS may try to recover the filesystem and may broke it
>>> completely.
>>
>> Does this apply to all spansion chips or only to selected few ?
>>
> 
> I've recently faced the very same issue with Winbond memories, which use
> the same procedure as Spansion to set the Quad Enable bit.
> More precisely, in my case it was some bare metal (bootloader) code but the
> issue was the same, there was no polling of busy bit from the Status
> Register after having set the QE bit in the Status Register 2 / Control
> Register 1. Then the next SPI command came too early and failed because the
> memory was actually still busy.
> 
> I faced this issue with Winbond W25Q256 and W25M512.

So we can leave this code as is ?

-- 
Best regards,
Marek Vasut