Re: [PATCH 5/8] mtd: spi-nor: spansion: Rework cypress_nor_quad_enable_volatile() for multi-chip device support

Takahiro Kuwano
2022-08-10T14:41:12Z

On 8/6/2022 3:34 PM, tkuw584924@gmail.com wrote:
> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>
> For multi-chip devices, we need to enable QUAD by updating CFR1V in all
> dice in the device. That is done by for-loop with params->num_of_dice.
> The volatile register address is calculated inside the loop by using die
> number and volatile register offset.
>
> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> ---
> drivers/mtd/spi-nor/spansion.c | 65 +++++++++++++++++-----------------
> 1 file changed, 33 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
> index d82dd750da9a..d7a61ea63139 100644
> --- a/drivers/mtd/spi-nor/spansion.c
> +++ b/drivers/mtd/spi-nor/spansion.c
> @@ -14,7 +14,7 @@
> #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
> #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
> #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
> -#define SPINOR_REG_CYPRESS_CFR1V 0x00800002
> +#define SPINOR_REG_CYPRESS_CFR1 0x2
> #define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN BIT(1) /* Quad Enable */
> #define SPINOR_REG_CYPRESS_CFR2V 0x00800003
> #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb
> @@ -137,46 +137,47 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
> static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
> {
> struct spi_mem_op op;
> + u32 addr;
> + u8 i;
> u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
> u8 cfr1v_written;
> int ret;
>
> - op = (struct spi_mem_op)
> - CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
> - SPINOR_REG_CYPRESS_CFR1V,
> - nor->bouncebuf);
> -
> - ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
> - if (ret)
> - return ret;
> + for (i = 0; i < nor->params->num_of_dice; i++) {
> + addr = nor->params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1;
> + op = (struct spi_mem_op)
> + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr,
> + nor->bouncebuf);
> + ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
> + if (ret)
> + return ret;
>
> - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN)
> - return 0;
> + if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN)
> + return 0;
Should be 'continue;'.

>
> - /* Update the Quad Enable bit. */
> - nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN;
> - op = (struct spi_mem_op)
> - CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
> - SPINOR_REG_CYPRESS_CFR1V, 1,
> - nor->bouncebuf);
> - ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
> - if (ret)
> - return ret;
> + /* Update the Quad Enable bit. */
> + nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN;
> + op = (struct spi_mem_op)
> + CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1,
> + nor->bouncebuf);
> + ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
> + if (ret)
> + return ret;
>
> - cfr1v_written = nor->bouncebuf[0];
> + cfr1v_written = nor->bouncebuf[0];
>
> - /* Read back and check it. */
> - op = (struct spi_mem_op)
> - CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
> - SPINOR_REG_CYPRESS_CFR1V,
> - nor->bouncebuf);
> - ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
> - if (ret)
> - return ret;
> + /* Read back and check it. */
> + op = (struct spi_mem_op)
> + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr,
> + nor->bouncebuf);
> + ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
> + if (ret)
> + return ret;
>
> - if (nor->bouncebuf[0] != cfr1v_written) {
> - dev_err(nor->dev, "CFR1: Read back test failed\n");
> - return -EIO;
> + if (nor->bouncebuf[0] != cfr1v_written) {
> + dev_err(nor->dev, "CFR1: Read back test failed\n");
> + return -EIO;
> + }
> }
>
> return 0;