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Mon, 23 Mar 2020 12:55:40 +0000 From: To: Subject: Re: [PATCH v3 4/5] mtd: spi-nor: Add SR 4bit block protection support Thread-Topic: [PATCH v3 4/5] mtd: spi-nor: Add SR 4bit block protection support Thread-Index: AQHWAPTegR7iigdWDECxp9El2paD96hWH0yAgAADfoA= Date: Mon, 23 Mar 2020 12:55:40 +0000 Message-ID: <8548006.u9pkoXE8D1@192.168.0.120> References: <20200323092430.1466234-1-tudor.ambarus@microchip.com> <20200323092430.1466234-6-tudor.ambarus@microchip.com> <26331bf950dc9945aad93f874dcf15d639fe3424.camel@samsung.com> In-Reply-To: <26331bf950dc9945aad93f874dcf15d639fe3424.camel@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tudor.Ambarus@microchip.com; x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a793b714-0ccb-4fe0-9ecd-08d7cf297da4 x-ms-traffictypediagnostic: BY5PR11MB4386: x-microsoft-antispam-prvs: x-bypassexternaltag: True x-ms-oob-tlc-oobclassifiers: OLM:9508; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On Monday, March 23, 2020 2:43:09 PM EET Jungseung Lee wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Hi, Hi, Jungseung, > > On Mon, 2020-03-23 at 09:24 +0000, Tudor.Ambarus@microchip.com wrote: > > From: Jungseung Lee > > > > Currently, we are supporting block protection only for flash chips > > with > > 3 block protection bits (BP0-2) in the SR register. > > > > Enable block protection support for flashes with 4 block protection > > bits > > (BP0-3). > > > > Add a flash_info flag for flashes that describe 4 block protection > > bits. > > Add another flash_info flag for flashes in which BP3 bit is not > > adjacent > > to the BP0-2 bits. > > > > Signed-off-by: Jungseung Lee > > Reviewed-by: Michael Walle > > Tested-by: Michael Walle > > [ta: > > - introduce spi_nor_get_sr_bp_mask(), spi_nor_get_sr_tb_mask() from the previous patch set > > - drop Micron n25q512ax3 / BP0-3) boilerplate description > > - be explicit in spi_nor_get_locked_range_sr aboyt SR_BP3 as Michael > > suggested, > > - amend commit description] I'll drop these comments when/if applying. Let me know if you're ok with the changes that I did. Please do the same for patches 3/5 and 5/5. > > Signed-off-by: Tudor Ambarus > > --- > > > > drivers/mtd/spi-nor/core.c | 66 +++++++++++++++++++++++++++------ > > > > ---- > > > > drivers/mtd/spi-nor/core.h | 10 ++++++ > > include/linux/mtd/spi-nor.h | 2 ++ > > 3 files changed, 60 insertions(+), 18 deletions(-) cut > Tested with a n25q512ax3 (bp0-3) and w25q128 (bp0-2). > It passed all of my test cases. > > Tested-by: Jungseung Lee Great! Since you are the author of the patch, it's not necessary to add your T-b tag, but I'll amend the commit description to say that it was tested on n25q512ax3 (bp0-3) and w25q128 (bp0-2). Also, would you please review patches 1 and 2 from the series? Cheers, ta ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/