From: Miquel Raynal <miquel.raynal@bootlin.com>
To: "Michael Walle" <mwalle@kernel.org>
Cc: "Pratyush Yadav" <pratyush@kernel.org>,
"Takahiro Kuwano" <takahiro.kuwano@infineon.com>,
"Richard Weinberger" <richard@nod.at>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
"Nicolas Ferre" <nicolas.ferre@microchip.com>,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
"Claudiu Beznea" <claudiu.beznea@tuxon.dev>,
"Steam Lin" <STLin2@winbond.com>,
"Hsin-Yi Wang" <hsinyi@chromium.org>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
<linux-mtd@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/5] mtd: spi-nor: Refactor Read Status/Write Status support
Date: Mon, 10 Aug 2026 16:05:59 +0200 [thread overview]
Message-ID: <875x1iqddk.fsf@bootlin.com> (raw)
In-Reply-To: <DKL2WROHNLXJ.3239EBUTVXRQL@kernel.org> (Michael Walle's message of "Mon, 10 Aug 2026 09:18:07 +0200")
On 10/08/2026 at 09:18:07 +02, "Michael Walle" <mwalle@kernel.org> wrote:
> On Thu Aug 6, 2026 at 9:38 AM CEST, Miquel Raynal wrote:
>> Hello Michael,
>>
>>>> One thing that comes to mind is hardware write protection. If
>>>> there's nothing before that code which checks it, the verify might
>>>> fail if the hardware write protection is enabled. So we should
>>>> somehow check for that and drop the verify here.
>>>
>>> But how do you think we should handle it? Will the QE bit writing
>>> verification fail if HW WP is enabled?
>
> It should, because you cannot alter the SR.
>
>> Looking into this further: we shall return an error if the QE bit is not
>> set. It just tells the caller that quad mode cannot be used. Then up to
>> the caller to either hard fail or just degrade into single mode (maybe
>> because of a strapped WP). What we should do is to propose a DT property
>> to flag when WP is strapped in hardware, this would make the content of
>> the status registers immutable and we would just skip the entire write
>> operation in the first place, instead of deliberately trying and get a
>> 100% failure rate. Nevertheless, the changes introduced here are kind of
>> orthogonal and do not alter the current behaviour; we shall however
>> listen if people start complaining about this and perhaps implement the
>> solution proposed above.
>
> There is already a property in the DT, where you almost certainly
> know that quad mode is impossible. Iff there are four rx/tx lines
> (spi-{rx,tx}-bus-width). I haven't seen a flash (even in larger
> packages) where there is a dedicated WP# pin.
>
> What do you mean by a dt property? If (1) the flash is using the WP#
> pin? Or (2) if it is using the WP# pin and it's tied to low?
>
> For (1) you have the QE bit, if it's set, WP is turned off and vice
> versa.
>
> For (2), that doesn't make sense, because that pin could be tied
> to some kind of logic which can change during runtime.
>
> FWIW, I don't care too much, you've asked why there is a
> verification step, I've just answered :)
Thank you :) Anyway, I've reinstated these checks in my last version.
If you look at it, don't focus on the commit about the names, I need to
fix that up again by adding some kind of "hide" flag for the RV chips,
instead of dropping the names (the rest won't change much).
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2026-08-10 14:06 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-29 16:05 [PATCH 0/5] mtd: spi-nor: Massive QE handling cleanup and Winbond RV chips addition Miquel Raynal
2026-05-29 16:05 ` [PATCH 1/5] mtd: spi-nor: Refactor Read Status/Write Status support Miquel Raynal
2026-07-07 9:43 ` Michael Walle
2026-08-04 14:57 ` Miquel Raynal
2026-08-05 14:04 ` Miquel Raynal
2026-08-10 6:50 ` Michael Walle
2026-08-06 7:38 ` Miquel Raynal
2026-08-10 7:18 ` Michael Walle
2026-08-10 14:05 ` Miquel Raynal [this message]
2026-05-29 16:05 ` [PATCH 2/5] mtd: spi-nor: Add support for the new JESD216 rev F QER field Miquel Raynal
2026-05-29 16:05 ` [PATCH 3/5] mtd: spi-nor: Move the SFDP header structure to a C header Miquel Raynal
2026-05-29 16:05 ` [PATCH 4/5] mtd: spi-nor: winbond: Add support for W25Q02RV-M Miquel Raynal
2026-05-29 16:05 ` [PATCH 5/5] mtd: spi-nor: winbond: Add support for W25Q51RV-M Miquel Raynal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=875x1iqddk.fsf@bootlin.com \
--to=miquel.raynal@bootlin.com \
--cc=STLin2@winbond.com \
--cc=alexandre.belloni@bootlin.com \
--cc=claudiu.beznea@tuxon.dev \
--cc=hsinyi@chromium.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=mwalle@kernel.org \
--cc=nicolas.ferre@microchip.com \
--cc=pratyush@kernel.org \
--cc=richard@nod.at \
--cc=takahiro.kuwano@infineon.com \
--cc=thomas.petazzoni@bootlin.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox