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Wed, 28 Oct 2026 16:39:45 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C4ABD103290D5; Wed, 28 Oct 2026 17:39:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1793205580; h=from:subject:date:message-id:to:cc:mime-version:content-type: in-reply-to:references; bh=d047tn7ZyUAE4CZJF6OwqmbdpCg4ZRFaWnDJv2Xlu+8=; b=qCMpHgryog1vBCpYw2HnRskue6gsLgB9uoaHyNvM0YNItQkxRCo1T8oI+12cGb5oxg6MgS EKhcVHkSpJmnXgfq03mwJGrHU6ylLbZNOshuzLyT1eTX31bfoylyj6RjFTeTa91PVNX3uA CFDxOIL63kdYVpkQfQtYyg/55KilXBl/VU1++SiVbKEjHIqY3qphAdZqMYGB+2bC8GGbl/ 4MOIDH9pwJEfT7Vdg+fVsuEpQIAxgZ3O10KHXWyo4M32AwlQ2xslc/Y1AAmDKDqMFHMV4q LTGC39X7sUZYIBe9gi1HS29LySxXbrl1x144YQZPz+lqRxwlrLlStqOmUUvgtQ== From: Miquel Raynal To: Changhuang Liang Cc: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Mark Brown , Richard Weinberger , Vignesh Raghavendra , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org Subject: Re: [PATCH v2 2/5] spi: dw: Add DDR (Dual Data-Rate) support for enhanced SPI mode In-Reply-To: <20261028121100.79667-3-changhuang.liang@starfivetech.com> (Changhuang Liang's message of "Wed, 28 Oct 2026 05:10:57 -0700") References: <20261028121100.79667-1-changhuang.liang@starfivetech.com> <20261028121100.79667-3-changhuang.liang@starfivetech.com> User-Agent: mu4e 1.12.12; emacs 30.2 Date: Wed, 28 Oct 2026 17:39:32 +0100 Message-ID: <87a4nxg4or.fsf@bootlin.com> X-Archived-By: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261028_093951_773419_C7C95D4F X-CRM114-Status: GOOD ( 15.07 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 28/10/2026 at 05:10:57 -07, Changhuang Liang wrote: > Add support for 1S-xD-xD DDR transfers in the enhanced SPI mode of the > DW SPI controller, on controllers that have DW_SPI_CAP_DDR. > > SPI_CTRLR0.SPI_DDR_EN switches the address, dummy and data phases to > DDR all together, and it only applies to the Dual/Quad/Octal frame > formats. So in supports_op() only accept DTR operations where the > command is sent in STR on one line, the data phase uses two lines or > more, and the address and dummy phases are DTR on the data lines. > DDR instruction phase (8D-8D-8D) is not supported for now. > > For DDR transfers the dummy phase takes two bits per clock on each > line, so the wait cycles must be halved. Factor the wait cycle > calculation into dw_spi_enh_wait_cycles(), so that supports_op() and > exec_op() use the same value, and refuse dummy phases that are not a > whole number of clock cycles. > > When DDR is enabled, program the DDR_DRIVE_EDGE register. The > recommended TDE value is SCKDV / 4, clamped to SCKDV / 2 - 1 and to > the field width. The register is only written when the controller > supports DDR. > > Finally, advertise DTR to the spi-mem layer through a dedicated > dw_spi_ddr_mem_caps when the controller has DW_SPI_CAP_DDR. > > Signed-off-by: Changhuang Liang Looks correct to me. Reviewed-by: Miquel Raynal ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/