From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Santhosh Kumar K <s-k6@ti.com>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <michael@walle.cc>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Steam Lin <stlin2@winbond.com>,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 01/21] mtd: spinand: Use more specific naming for the reset op
Date: Thu, 20 Mar 2025 12:31:55 +0100 [thread overview]
Message-ID: <87msdgvsyc.fsf@bootlin.com> (raw)
In-Reply-To: <ba99ef52-0c98-45a9-91e0-4fd205649e00@linaro.org> (Tudor Ambarus's message of "Thu, 20 Mar 2025 08:08:50 +0000")
>>> How do you feel about a OP-An-Bn-Cn-transaction-format,
>>> where A, B, C is {1, 2, 4, 8}
>>> n is {S, D}
>>> transaction format is {0,1,2,3}{A,B,C,...}
>>>
>>> Care must be taken care of at the transaction format, as I see there are
>>> a few, depending on the xSPI profile and protocol mode.
>>
>> I must admit I really dislike the transaction format abbreviation because
>
> I'm not in love with the "transaction format" either.
>
>> it is specific to a spec we do not follow and is not explicit. I have a
>> strong preference towards keeping just "An-Bn-Cn", like I did in this
>
> Okay.
>
>> series. If people are in doubt, they can check what is in the op, it is
>> self explanatory. I chose this in the first place because it is more
>> explicit than just "An" which may feel like a cropped
>> acronym. Furthermore, most octal capable datasheets I've looked at seem
>> to use the "An-Bn-Cn" format, even for single opcodes.
>
> So for RESET, WREN, WRDI and other opcodes that don't require address
> and data, are those datasheets referring to these opcodes as 1-1-1 commands?
> Can you point me to one of these datasheets, please?
All Winbond datasheets use this convention:
https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf
See 7.1.2 Instruction Set Table p.25.
I checked Macronix and Gigadevice datasheets, they simply never "name"
these opcodes clearly.
> In SPI NOR, WREN is just WREN, regardless of the number of lines it is
> sent on, 1, 4, or 8. How would you model it here, 1-0-0, 4-0-0, 8-0-0
> using the same opcode?
I guess, yes.
>> So unless there are strong arguments against, I'd prefer to keep the
>> current formatting. TBH, it is not set in stone and can still evolve
>> later if that's needed.
>
> I find the naming scheme An-Bn-Cn good, I'm arguing that it's not needed
> everywhere, opcode only commands are better off with it, I think.
Ok, I can drop the -0-0 in this case if you prefer.
Thanks,
Miquèl
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next prev parent reply other threads:[~2025-03-20 11:32 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-07 15:08 [PATCH 00/21] mtd: spinand: Add octal support Miquel Raynal
2025-03-07 15:08 ` [PATCH 01/21] mtd: spinand: Use more specific naming for the reset op Miquel Raynal
2025-03-07 15:38 ` Tudor Ambarus
2025-03-07 15:45 ` Miquel Raynal
2025-03-10 10:14 ` Tudor Ambarus
2025-03-19 17:32 ` Miquel Raynal
2025-03-20 8:08 ` Tudor Ambarus
2025-03-20 11:31 ` Miquel Raynal [this message]
2025-03-20 12:03 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 02/21] mtd: spinand: Use more specific naming for the write enable/disable op Miquel Raynal
2025-03-07 15:39 ` Tudor Ambarus
2025-03-07 15:49 ` Miquel Raynal
2025-03-20 12:22 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 03/21] mtd: spinand: Use more specific naming for the read ID op Miquel Raynal
2025-03-07 15:40 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 04/21] mtd: spinand: Use more specific naming for the get/set feature ops Miquel Raynal
2025-03-07 15:42 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 05/21] mtd: spinand: Use more specific naming for the erase op Miquel Raynal
2025-03-07 15:45 ` Tudor Ambarus
2025-03-07 16:03 ` Miquel Raynal
2025-03-20 12:23 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 06/21] mtd: spinand: Use more specific naming for the page read op Miquel Raynal
2025-03-20 12:28 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 07/21] mtd: spinand: Use more specific naming for the (single) read from cache ops Miquel Raynal
2025-04-02 15:05 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 08/21] mtd: spinand: Use more specific naming for the (dual output) " Miquel Raynal
2025-04-02 15:06 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 09/21] mtd: spinand: Use more specific naming for the (dual IO) " Miquel Raynal
2025-04-02 15:07 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 10/21] mtd: spinand: Use more specific naming for the (quad output) " Miquel Raynal
2025-04-02 15:07 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 11/21] mtd: spinand: Use more specific naming for the (quad IO) " Miquel Raynal
2025-04-02 15:08 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 12/21] mtd: spinand: Use more specific naming for the program execution op Miquel Raynal
2025-04-02 15:12 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 13/21] mtd: spinand: Use more specific naming for the (single) program load op Miquel Raynal
2025-04-02 15:13 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 14/21] mtd: spinand: Use more specific naming for the (quad) " Miquel Raynal
2025-04-02 15:13 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 15/21] mtd: spinand: winbond: Rename DTR variants Miquel Raynal
2025-04-02 15:19 ` Tudor Ambarus
2025-04-02 16:57 ` Miquel Raynal
2025-04-03 6:19 ` Tudor Ambarus
2025-04-03 8:53 ` Miquel Raynal
2025-04-03 9:48 ` Tudor Ambarus
2025-03-07 15:08 ` [PATCH 16/21] mtd: spinand: winbond: Add support for W35N01JW in single mode Miquel Raynal
2025-04-02 15:22 ` Tudor Ambarus
2025-04-02 17:06 ` Miquel Raynal
2025-03-07 15:08 ` [PATCH 17/21] mtd: spinand: Define octal read from cache operations Miquel Raynal
2025-03-07 15:08 ` [PATCH 18/21] mtd: spinand: winbond: Add octal read support Miquel Raynal
2025-03-07 15:08 ` [PATCH 19/21] mtd: spinand: Define octal load to cache operations Miquel Raynal
2025-03-07 15:08 ` [PATCH 20/21] mtd: spinand: winbond: Add octal program support Miquel Raynal
2025-03-07 15:08 ` [PATCH 21/21] mtd: spinand: winbond: Add support for W35N02JW and W35N02JW chips Miquel Raynal
2025-04-02 15:25 ` Tudor Ambarus
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