From: Miquel Raynal <miquel.raynal@bootlin.com>
To: James Hilliard <james.hilliard1@gmail.com>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Chen-Yu Tsai <wens@kernel.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Maxime Ripard <mripard@kernel.org>,
Richard Genoud <richard.genoud@bootlin.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Boris Brezillon <bbrezillon@kernel.org>,
Brian Norris <computersforpeace@gmail.com>,
linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
stable@vger.kernel.org
Subject: Re: [PATCH v6 01/18] mtd: rawnand: sunxi: drain interrupts before reusing the completion
Date: Mon, 12 Oct 2026 22:53:22 +0200 [thread overview]
Message-ID: <87pkxey725.fsf@bootlin.com> (raw)
In-Reply-To: <CADvTj4ppQannShF+dkLreST94g_vSAg4QdMqxhNORzkvci3O1A@mail.gmail.com> (James Hilliard's message of "Mon, 12 Oct 2026 13:17:23 -0600")
>> >> commit log, I now disagree with the first part of:
>> >>
>> >> >The old handler can also complete the new wait or restore an obsolete interrupt mask.
>> >>
>> >> "complete the new wait"? I don't see how a stale handler completes the
>> >> next wait given the handler is a hard IRQ and the interrupt enable
>> >> register is cleared on timeout.
>> >
>> > The case I had in mind is an already-running handler on another CPU:
>> >
>> > CPU 0: Read st and ien for operation A.
>> > CPU 1: Time out operation A, mask/acknowledge its interrupts,
>> > then eventually reinitialize the completion for operation B.
>> > CPU 0: Call complete() based on the saved st and ien from operation A.
>>
>> For this to fire, the hard IRQ handler on CPU0 would have to be stopped
>> between reading st/ien and calling complete() long enough to span:
>> - A's timeout
>> - A's cleanup
>> - B's wait being rearmed
>> On this hardware, how is this reachable?
>
> CONFIG_PREEMPT_RT provides a concrete mechanism. The driver requests this
> IRQ with flags = 0, without IRQF_NO_THREAD, so the handler is
> forced-threaded. A higher-priority task can preempt that IRQ thread
> after it reads st/ien:
That argument only appears in this reply. It is not in the commit log
nor in the diff, both of which reason about a hard IRQ, no? I'll happily
take the PREEMPT_RT case into account: in that configuration the case is
reachable, but it reads as a justification added after the fact.
Then, I'm curious to know how the AI justifies the use of disable_irq()
as the RT-appropriate choice: doesn't it block without a timeout on the
very IRQ thread the scenario relies on being starved (and gives no
priority inheritance)?
Thanks,
Miquèl
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next prev parent reply other threads:[~2026-10-12 20:53 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-14 21:09 [PATCH v6 00/18] mtd: rawnand: sunxi: support the Allwinner randomized OOB format James Hilliard
2026-09-14 21:09 ` [PATCH v6 01/18] mtd: rawnand: sunxi: drain interrupts before reusing the completion James Hilliard
2026-10-12 18:01 ` Miquel Raynal
2026-10-12 18:26 ` James Hilliard
2026-10-12 19:06 ` Miquel Raynal
2026-10-12 19:17 ` James Hilliard
2026-10-12 20:53 ` Miquel Raynal [this message]
2026-10-12 21:43 ` James Hilliard
2026-09-14 21:09 ` [PATCH v6 02/18] mtd: rawnand: sunxi: use the logical step's OOB length in PIO James Hilliard
2026-09-14 21:09 ` [PATCH v6 03/18] mtd: rawnand: sunxi: propagate page-setup and erased-check errors James Hilliard
2026-09-14 21:09 ` [PATCH v6 04/18] mtd: rawnand: sunxi: stop failed program operations and disable ECC James Hilliard
2026-09-14 21:09 ` [PATCH v6 05/18] mtd: rawnand: sunxi: select the pattern ID for the current ECC step James Hilliard
2026-09-14 21:09 ` [PATCH v6 06/18] mtd: rawnand: sunxi: propagate buffer and column transfer errors James Hilliard
2026-09-14 21:09 ` [PATCH v6 07/18] mtd: rawnand: sunxi: avoid a second program confirm for OOB writes James Hilliard
2026-09-14 21:09 ` [PATCH v6 08/18] mtd: rawnand: sunxi: avoid redundant column changes for extra OOB James Hilliard
2026-09-14 21:09 ` [PATCH v6 09/18] mtd: rawnand: sunxi: use page reads to reposition small-page NAND James Hilliard
2026-09-14 21:09 ` [PATCH v6 10/18] mtd: rawnand: sunxi: bound DMA batches by the user-data register bank James Hilliard
2026-09-14 21:09 ` [PATCH v6 11/18] mtd: rawnand: sunxi: clarify OOB register and step handling James Hilliard
2026-09-14 21:09 ` [PATCH v6 12/18] dt-bindings: mtd: sunxi: Add randomized OOB flag James Hilliard
2026-09-15 16:56 ` Conor Dooley
2026-09-14 21:09 ` [PATCH v6 13/18] mtd: rawnand: sunxi: support randomized OOB formats James Hilliard
2026-09-14 21:10 ` [PATCH v6 14/18] mtd: rawnand: sunxi: select the packed H6/H616 OOB layout James Hilliard
2026-09-14 21:10 ` [PATCH v6 15/18] mtd: rawnand: sunxi: combine contiguous unprotected OOB reads James Hilliard
2026-09-14 21:10 ` [PATCH v6 16/18] mtd: rawnand: sunxi: avoid duplicate chip setup before page commands James Hilliard
2026-09-14 21:10 ` [PATCH v6 17/18] mtd: rawnand: sunxi: reduce user-data length register accesses James Hilliard
2026-09-14 21:10 ` [PATCH v6 18/18] mtd: rawnand: sunxi: reuse ECC status within each DMA read James Hilliard
2026-10-12 8:06 ` [PATCH v6 00/18] mtd: rawnand: sunxi: support the Allwinner randomized OOB format Miquel Raynal
2026-10-12 8:56 ` James Hilliard
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