From: <Tudor.Ambarus@microchip.com>
To: <bbrezillon@kernel.org>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
alexandre.belloni@bootlin.com, broonie@kernel.org,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
Ludovic.Desroches@microchip.com, robh+dt@kernel.org,
linux-mtd@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 10/10] spi: atmel-quadspi: add support for sam9x60 qspi controller
Date: Fri, 1 Feb 2019 14:49:27 +0000 [thread overview]
Message-ID: <8b935a95-0aaa-3430-e2c2-f5793fd9cf11@microchip.com> (raw)
In-Reply-To: <20190201085739.775add3f@bbrezillon>
On 02/01/2019 09:57 AM, Boris Brezillon wrote:
> On Fri, 1 Feb 2019 07:07:40 +0000
> <Tudor.Ambarus@microchip.com> wrote:
>
>>>
>>>> #define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12)
>>>> #define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12)
>>>> #define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12)
>>>
>>> Looks like the read/write flag is on bit 13. Can we just add
>>
>> for sama5d2 only
>
> Feel free to prefix macros with the SoC name to make it clear:
>
> #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
agreed
>
cut
>>>> +#define QSPI_IFR_APBTFRTYP_READ BIT(24)
>
> And this one would be
>
> define QSPI_IFR_SAM9X60_READ_TRSFR BIT(24)
I prefer letting this bit named as in the datasheet, QSPI_IFR_APBTFRTYP_READ,
and change it if future versions of the IP will modify its sense. It is a READ
transfer done on APB, it is more generic this way. If you have a strong opinion
on this, please let me know.
ta
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next prev parent reply other threads:[~2019-02-01 14:49 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-31 16:15 [PATCH v2 00/10] spi: atmel-quadspi: introduce sam9x60 qspi controller Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 01/10] spi: atmel-quadspi: cache MR value to avoid a write access Tudor.Ambarus
2019-01-31 16:55 ` Boris Brezillon
2019-02-01 6:51 ` Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 02/10] spi: atmel-quadspi: order header files inclusion alphabetically Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 03/10] spi: atmel-quadspi: drop wrappers for iomem accesses Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 04/10] spi: atmel-quadspi: fix naming scheme Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 05/10] spi: atmel-quadspi: remove unnecessary cast Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 06/10] spi: atmel-quadspi: return appropriate error code Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 07/10] spi: atmel-quadspi: switch to SPDX license identifiers Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 08/10] dt-bindings: spi: atmel-quadspi: update example to new clock binding Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 09/10] dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60 Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 10/10] spi: atmel-quadspi: add support for sam9x60 qspi controller Tudor.Ambarus
2019-01-31 16:32 ` Boris Brezillon
2019-02-01 7:07 ` Tudor.Ambarus
2019-02-01 7:57 ` Boris Brezillon
2019-02-01 14:49 ` Tudor.Ambarus [this message]
2019-02-01 15:45 ` Boris Brezillon
2019-02-01 14:43 ` Tudor.Ambarus
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