M-Sys Reed Solomon

["Miguel Freitas" <miguel@cetuc.puc-rio.br>]

    Hi Patrick,

    I'm trying to understand the M-Systems Reed Solomon 
implementation used in DiskOnChip, maybe we could exchange 
some ideas... how is it going the code?

    I read your email when you went for vacation, more than a month 
ago. I have some comments on it, probably old ones for you, but 
let's try...
    1) How do you know that these 4 x ten bit word encoded in that 6 
interleaved bytes are actually the syndrom? It doesn't make sense 
for me... First, a syndrom should be zero for a correct block and 
second, they always transmit the ECC "parity" and never the 
syndrom itself. The syndrom is computed from the whole codeword 
(data+parity)...(apologize me if I'm stating the obvious).
    2) Where did you get the information to convert the 6 interleaved 
bytes into 4 x ten bit word? The parallel 8 bit parity at the second 
byte is easy to see, but the 40 bits could be arranged in a different 
manner under 5 bytes. The M-Sys driver has a routine to do that 
conversion, but in another sequence (and without the parallel parity).
    3) I guess you should have already figured out what is the 
primitive polynomial they use. Just in case, it's the classical 
x^10+x^3+1. This became clear with a little reverse engineering...

    I also tryed to match the hardware ECC data initializing the shift 
register encoder with symbols different than zero without success. 
Have you had more lucky in the last month?


Regards,

Miguel Freitas



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