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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id bb8sm629332oib.9.2021.12.01.15.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Dec 2021 15:20:21 -0800 (PST) Received: (nullmailer pid 3150169 invoked by uid 1000); Wed, 01 Dec 2021 23:20:20 -0000 Date: Wed, 1 Dec 2021 17:20:20 -0600 From: Rob Herring To: Miquel Raynal Cc: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, Mark Brown , linux-spi@vger.kernel.org, Xiangsheng Hou , Julien Su , Jaime Liao , Boris Brezillon , Thomas Petazzoni Subject: Re: [PATCH v2 03/20] dt-bindings: mtd: nand-chip: Create a NAND chip description Message-ID: References: <20211126113924.310459-1-miquel.raynal@bootlin.com> <20211126113924.310459-4-miquel.raynal@bootlin.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211126113924.310459-4-miquel.raynal@bootlin.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211201_152023_317964_AE842783 X-CRM114-Status: GOOD ( 26.53 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On Fri, Nov 26, 2021 at 12:39:07PM +0100, Miquel Raynal wrote: > Move the NAND chip description out of the NAND controller file. Indeed, > a subsequent part of the properties supported by a raw NAND chip are > also supported by SPI-NAND chips. So let's create a generic NAND chip > description which will be pulled by nand-controller.yaml and later by > spi-nand.yaml as well. > > Signed-off-by: Miquel Raynal > --- > .../devicetree/bindings/mtd/nand-chip.yaml | 71 +++++++++++++++++++ > .../bindings/mtd/nand-controller.yaml | 53 ++------------ > 2 files changed, 75 insertions(+), 49 deletions(-) > create mode 100644 Documentation/devicetree/bindings/mtd/nand-chip.yaml > > diff --git a/Documentation/devicetree/bindings/mtd/nand-chip.yaml b/Documentation/devicetree/bindings/mtd/nand-chip.yaml > new file mode 100644 > index 000000000000..6d13e8cdbb21 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/nand-chip.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mtd/nand-chip.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NAND Chip and NAND Controller Generic Binding > + > +maintainers: > + - Miquel Raynal > + > +description: | > + This file covers the generic description of a NAND chip. It implies that the > + bus interface should not be taken into account: both raw NAND devices and > + SPI-NAND devices are concerned by this description. > + > +properties: > + reg: > + description: > + Contains the chip-select IDs. > + > + nand-ecc-engine: > + allOf: Can you drop the allOf here. > + - $ref: /schemas/types.yaml#/definitions/phandle > + description: | > + A phandle on the hardware ECC engine if any. There are > + basically three possibilities: > + 1/ The ECC engine is part of the NAND controller, in this > + case the phandle should reference the parent node. > + 2/ The ECC engine is part of the NAND part (on-die), in this > + case the phandle should reference the node itself. > + 3/ The ECC engine is external, in this case the phandle should > + reference the specific ECC engine node. > + > + nand-use-soft-ecc-engine: > + type: boolean > + description: Use a software ECC engine. > + > + nand-no-ecc-engine: > + type: boolean > + description: Do not use any ECC correction. > + > + nand-ecc-algo: > + description: > + Desired ECC algorithm. > + $ref: /schemas/types.yaml#/definitions/string > + enum: [hamming, bch, rs] > + > + nand-ecc-strength: > + description: > + Maximum number of bits that can be corrected per ECC step. > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 1 > + > + nand-ecc-step-size: > + description: > + Number of data bytes covered by a single ECC step. > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 1 > + > + secure-regions: > + $ref: /schemas/types.yaml#/definitions/uint64-matrix > + description: > + Regions in the NAND chip which are protected using a secure element > + like Trustzone. This property contains the start address and size of > + the secure regions present. > + > +required: > + - reg > + > +additionalProperties: true > diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml > index 5cd144a9ec99..44825dc95412 100644 > --- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml > +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml > @@ -52,32 +52,15 @@ properties: > patternProperties: > "^nand@[a-f0-9]$": > type: object > + > + allOf: Also not needed here. With that, Reviewed-by: Rob Herring > + - $ref: "nand-chip.yaml#" > + ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/