From: Mark Brown <broonie@kernel.org>
To: "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@amd.com>
Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>,
"p.yadav@ti.com" <p.yadav@ti.com>,
"miquel.raynal@bootlin.com" <miquel.raynal@bootlin.com>,
"richard@nod.at" <richard@nod.at>,
"vigneshr@ti.com" <vigneshr@ti.com>,
"git@xilinx.com" <git@xilinx.com>,
"michal.simek@xilinx.com" <michal.simek@xilinx.com>,
"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"michael@walle.cc" <michael@walle.cc>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"git (AMD-Xilinx)" <git@amd.com>
Subject: Re: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI device
Date: Thu, 23 Jun 2022 13:06:38 +0100 [thread overview]
Message-ID: <YrRXTrYN3BuShbzg@sirena.org.uk> (raw)
In-Reply-To: <DM6PR12MB2809F6C7D80B60556218D627DCB59@DM6PR12MB2809.namprd12.prod.outlook.com>
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On Thu, Jun 23, 2022 at 11:39:19AM +0000, Mahapatra, Amit Kumar wrote:
> > > /* Mode (clock phase/polarity/etc.) */
> > > if (of_property_read_bool(nc, "spi-cpha"))
> > This is changing the DT binding but doesn't have any updates to the binding
> > document. The binding code also doesn't validate that we don't have too
> > many chip selects.
> The following updates are done in the binding documents for adding multiple
> CS support:
> In jedec,spi-nor.yaml file " maxItems " of the "reg" DT property has been
> updated to accommodate two CS per SPI device.
This is a change to a binding for a specific driver, this is changing
the SPI core.
> > I'm also not seeing anything here that checks that the driver supports
> > multiple chip selects - it seems like something that's going to cause issues
> > and we should probably have something to handle that situation.
> In my approach the chip select member (chip_select) of the spi_device structure
> is changed to an array (chip_select[2]). This array is used to store the CS values
> coming from the "reg" DT property.
> In case of multiple chip selects spi->chip_slect[0] will hold CS0 value &
> spi->chip_select[1] wil hold CS1 value.
> In case of single chip select the spi->chip_select[0] will hold the chip select value.
That doesn't address the issue, the issue is checking that the driver
can support multiple chip selects.
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next prev parent reply other threads:[~2022-06-23 12:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-06 11:26 [RFC PATCH 0/2] spi: Add support for stacked/parallel memories Amit Kumar Mahapatra
2022-06-06 11:26 ` [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI device Amit Kumar Mahapatra
2022-06-09 11:54 ` Mark Brown
2022-06-23 11:39 ` Mahapatra, Amit Kumar
2022-06-23 12:06 ` Mark Brown [this message]
2022-07-15 15:35 ` Mahapatra, Amit Kumar
2022-07-15 15:54 ` Mark Brown
2022-07-19 13:21 ` Mahapatra, Amit Kumar
2022-07-19 17:53 ` Mark Brown
2022-07-27 13:02 ` Mahapatra, Amit Kumar
2022-07-11 12:47 ` Michal Simek
2022-07-11 14:52 ` Mark Brown
2022-07-15 15:36 ` Mahapatra, Amit Kumar
2022-07-15 16:03 ` Mark Brown
2022-06-06 11:26 ` [RFC PATCH 2/2] mtd: spi-nor: Add support for stacked/parallel memories Amit Kumar Mahapatra
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