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Date: Fri, 25 Jul 2003 17:12:36 +0200
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From: "J.D. Bakker" <bakker@thorgal.et.tudelft.nl>
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Subject: Handling multiple NAND chips
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Hi all,

I have an expansion board for the LART (an embedded computer based on 
the DEC/Intel StrongARM) with eight NAND flash devices on it. As 
suggested by the Toshiba datasheet, they share data, CLE, ALE, nWE 
and nRE and RDY. Each chip has its own nCE line.

I would like to use all eight chips with mtdconcat and YAFFS. Given 
the above, how should I hook the eight NANDs up to the mtd layer ? 
I've gone through CVS, but haven't found any hints in The Source.

By the way, is mtd multi-threaded whne using multiple devices ? 
Should I worry about overlapping address/data phases to separate NAND 
chips ?

Thanks,

Jan-Derk Bakker
[who inflicted the LART_ENDIAN_BYTE ordering on mtd]
-- 
LART. 250 MIPS under one Watt. Free hardware design files.
http://www.lart.tudelft.nl/