Re: [PATCH v3 4/6] mtd: spi-nor: spansion: Add support for volatile QE bit

[Takahiro Kuwano <tkuw584924@gmail.com>]

On 3/18/2021 5:19 PM, Pratyush Yadav wrote:
> On 18/03/21 05:00PM, Takahiro Kuwano wrote:
>> On 3/15/2021 8:47 PM, Pratyush Yadav wrote:
>>> On 12/03/21 06:44PM, tkuw584924@gmail.com wrote:
>>>> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>>>
>>>> Some of Spansion/Cypress chips support volatile version of configuration
>>>> registers and it is recommended to update volatile registers in the field
>>>> application due to a risk of the non-volatile registers corruption by
>>>> power interrupt. This patch adds a function to set Quad Enable bit in CFR1
>>>> volatile. The function supports multi-die package parts that require to
>>>> set the Quad Enable bit in each die.
>>>>
>>>> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>>> ---
>>>> Changes in v3:
>>>>   - Add multi-die package parts support
>>>>
>>>>  drivers/mtd/spi-nor/spansion.c | 58 ++++++++++++++++++++++++++++++++++
>>>>  1 file changed, 58 insertions(+)
>>>>
>>>> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
>>>> index 1bce95cb7896..b5b5df4836c6 100644
>>>> --- a/drivers/mtd/spi-nor/spansion.c
>>>> +++ b/drivers/mtd/spi-nor/spansion.c
>>>> @@ -10,6 +10,8 @@
>>>>  
>>>>  #define SPINOR_OP_RD_ANY_REG			0x65	/* Read any register */
>>>>  #define SPINOR_OP_WR_ANY_REG			0x71	/* Write any register */
>>>> +#define SPINOR_REG_CYPRESS_CFR1V		0x00800002
>>>> +#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN	BIT(1)	/* Quad Enable */
>>>>  #define SPINOR_REG_CYPRESS_CFR2V		0x00800003
>>>>  #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24	0xb
>>>>  #define SPINOR_REG_CYPRESS_CFR3V		0x00800004
>>>> @@ -121,6 +123,62 @@ static int spansion_write_any_reg(struct spi_nor *nor, u32 reg_addr, u8 reg_val)
>>>>  	return ret;
>>>>  }
>>>>  
>>>> +/**
>>>> + * spansion_quad_enable_volatile() - enable Quad I/O mode in volatile register.
>>>> + * @nor:	pointer to a 'struct spi_nor'
>>>> + * @reg_dummy:	number of dummy cycles for register read
>>>> + * @die_size:	size of each die to determine the number of dies
>>>> + *
>>>> + * It is recommended to update volatile registers in the field application due
>>>> + * to a risk of the non-volatile registers corruption by power interrupt. This
>>>> + * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable
>>>> + * bit in the CFR1 non-volatile in advance (typically by a Flash programmer
>>>> + * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is
>>>> + * also set during Flash power-up. This function supports multi-die package
>>>> + * parts that require to set the Quad Enable bit in each die.
>>>> + *
>>>> + * Return: 0 on success, -errno otherwise.
>>>> + */
>>>> +static int spansion_quad_enable_volatile(struct spi_nor *nor, u8 reg_dummy,
>>>> +					 u32 die_size)
>>>> +{
>>>> +	int ret;
>>>> +	u32 base, reg_addr;
>>>> +	u8 cfr1v, cfr1v_written;
>>>> +
>>>> +	for (base = 0; base < nor->params->size; base += die_size) {
>>>> +		reg_addr = base + SPINOR_REG_CYPRESS_CFR1V;
>>>> +
>>>> +		ret = spansion_read_any_reg(nor, reg_addr, reg_dummy, &cfr1v);
>>>
>>> I didn't notice it when reviewing the U-Boot series. How does register 
>>> read work here? This will be issued in 1-1-4 mode since the 
>>> nor->read_proto should be set to that protocol. But the flash is still 
>>> in 1-1-1 mode. So the flash will output data on 1 line and the 
>>> controller will read it on 4 lines, giving us a bogus register value. In 
>>> fact I see this with pretty much every quad_enable() hook. What am I 
>>> missing?
>>>
>> The nor->reg_proto is used for register access and it is 1-1-1 at this
>> point.
> 
> Ah, right. Also...
> 
>>
>>>> +		if (ret)
>>>> +			return ret;
>>>> +
>>>> +		if (cfr1v & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN)
>>>> +			continue;
>>>> +
>>>> +		/* Update the Quad Enable bit. */
>>>> +		cfr1v |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN;
>>>> +
>>>> +		ret = spansion_write_any_reg(nor, reg_addr, cfr1v);
>>>> +		if (ret)
>>>> +			return ret;
>>>> +
>>>> +		cfr1v_written = cfr1v;
>>>> +
>>>> +		/* Read back and check it. */
>>>> +		ret = spansion_read_any_reg(nor, reg_addr, reg_dummy, &cfr1v);
>>>> +		if (ret)
>>>> +			return ret;
> 
> ... this would still send data in 1-1-1 even after quad mode being 
> enabled, right? If so,
> 
> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
> 
Yes, the Flash works in 1-1-1 for register access even if quad mode
is enabled.

Best Regards,
Takahiro

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