Re: [PATCH v5 2/4] mtd: rawnand: meson: fix the clock

[Liang Yang <liang.yang@amlogic.com>]

Hi Kevin,

Thanks for your review.

On 2022/5/27 0:28, Kevin Hilman wrote:
> [ EXTERNAL EMAIL ]
> 
> Hi Liang,
> 
> Liang Yang <liang.yang@amlogic.com> writes:
> 
>> EMMC and NAND have the same clock control register named 'SD_EMMC_CLOCK'
>> which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is
>> the divider and bit6~7 is the mux for fix pll and xtal. At the beginning,
>> a common MMC and NAND sub-clock was discussed and planed to be implemented
>> as NFC clock provider, but now this series of patches of a common MMC and
>> NAND sub-clock are never being accepted.  the reasons for giving up are:
>> 1. EMMC and NAND, which are mutually exclusive anyway
>> 2. coupling the EMMC and NAND.
>> 3. it seems that a common MMC and NAND sub-clock is over engineered.
>> and let us see the link fot more information:
>> https://lore.kernel.org/all/20220121074508.42168-5-liang.yang@amlogic.com
>> so The meson nfc can't work now, let us rework the clock.
>>
>> Signed-off-by: Liang Yang <liang.yang@amlogic.com>
> 
> Reviewed-by: Kevin Hilman <khilman@baylibre.com>
> 
> Thank you for your persistence in working on multiple iterations of this
> until we came to a final agreement.
> 
> Kevin
> 
> .

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