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From: Michael Walle <michael@walle.cc>
To: Takahiro Kuwano <tkuw584924@gmail.com>
Cc: Tudor.Ambarus@microchip.com, Takahiro.Kuwano@infineon.com,
	juliensu@mxic.com.tw, jaimeliao@mxic.com.tw,
	Bacem.Daassi@infineon.com, beanhuo@micron.com,
	shiva.linuxworks@gmail.com, sshivamurthy@micron.com,
	p.yadav@ti.com, linux-mtd@lists.infradead.org
Subject: Re: How does an SPI NOR handle a single byte write in Octal DTR mode?
Date: Mon, 20 Dec 2021 16:47:45 +0100	[thread overview]
Message-ID: <a7bd7dc6db2cb9f74aa6e7737e888625@walle.cc> (raw)
In-Reply-To: <d40c879c-c419-82c4-c385-0a03e105a622@gmail.com>

Hi,

Am 2021-12-20 11:32, schrieb Takahiro Kuwano:
> In case of Infineon(Cypress) S28 devices, it can be done by 
> de-asserting
> chip select before clock falling (not sure typical controllers support 
> this).
> That means the device can take odd address in 8D-8D-8D mode.

Ahh nice. FWIW, I had a quick look at the FlexSPI controller found on
the NXP LS1028A, it doesn't seem to support deasserting the CS after
half a clock cycle, though.

-michael

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  reply	other threads:[~2021-12-20 15:48 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-20  9:36 How does an SPI NOR handle a single byte write in Octal DTR mode? Tudor.Ambarus
2021-12-20 10:32 ` Takahiro Kuwano
2021-12-20 15:47   ` Michael Walle [this message]
2021-12-21 23:32     ` Takahiro Kuwano

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