Re: How does an SPI NOR handle a single byte write in Octal DTR mode?

Takahiro Kuwano
2021-12-21T23:33:10Z

Hi,

I need to correct my previous statement.

On 12/21/2021 12:47 AM, Michael Walle wrote:
> Hi,
>
> Am 2021-12-20 11:32, schrieb Takahiro Kuwano:
>> In case of Infineon(Cypress) S28 devices, it can be done by de-asserting
>> chip select before clock falling (not sure typical controllers support this).
This is true for single-byte register write op.

>> That means the device can take odd address in 8D-8D-8D mode.
For page program op, the S28 in 8D-8D-8D mode only supports programming
multiples of 2-bytes and the address must start at an even address.

>
> Ahh nice. FWIW, I had a quick look at the FlexSPI controller found on
> the NXP LS1028A, it doesn't seem to support deasserting the CS after
> half a clock cycle, though.
>
> -michael

Thanks,
Takahiro