From: Michael Walle <mwalle@kernel.org>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Jaime Liao <jaimeliao.tw@gmail.com>,
linux-mtd@lists.infradead.org, pratyush@kernel.org,
miquel.raynal@bootlin.com, leoyu@mxic.com.tw,
jaimeliao@mxic.com.tw
Subject: Re: [PATCH v2] mtd: spi-nor: core: Discard HW capabilities if no enable function
Date: Wed, 20 Dec 2023 09:43:16 +0100 [thread overview]
Message-ID: <aa887159f4d80d575a25a5ae0bc86a19@kernel.org> (raw)
In-Reply-To: <b33b7841-d68e-4576-b8e5-72eab04fce2d@linaro.org>
Am 2023-12-20 09:07, schrieb Tudor Ambarus:
> On 19.12.2023 12:21, Jaime Liao wrote:
>> From: JaimeLiao <jaimeliao@mxic.com.tw>
>>
>> Discard corresponding HW capabilities to prevent carrying the
>> wrong protocol if no QUAD/Octal DTR enable function hooked.
>>
>> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
>> ---
>> changes in v2
>> - Add SNOR_HWCAPS_8_8_8_DTR
>> - Restore the enable function judgement in spi_nor_set_octal_dtr()
>> - Restore the enable function judgement in spi_nor_quad_enable()
>> ---
>> drivers/mtd/spi-nor/core.c | 7 +++++++
>> include/linux/mtd/spi-nor.h | 6 ++++++
>> 2 files changed, 13 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
>> index 1c443fe568cf..14359101c6cf 100644
>> --- a/drivers/mtd/spi-nor/core.c
>> +++ b/drivers/mtd/spi-nor/core.c
>> @@ -2621,6 +2621,13 @@ static int spi_nor_default_setup(struct spi_nor
>> *nor,
>> */
>> shared_mask = hwcaps->mask & params->hwcaps.mask;
>>
>> + /* Mask out Octal DTR if no enable function */
>> + if (!params->set_octal_dtr)
>> + shared_mask &= ~SNOR_HWCAPS_8_8_8_DTR;
>> +
>> + if (!params->quad_enable)
>> + shared_mask &= ~SNOR_HWCAPS_4_4_4;
>> +
>> if (nor->spimem) {
>> /*
>> * When called from spi_nor_probe(), all caps are set and we
>> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
>> index cdcfe0fd2e7d..78a119192ee0 100644
>> --- a/include/linux/mtd/spi-nor.h
>> +++ b/include/linux/mtd/spi-nor.h
>> @@ -266,6 +266,12 @@ struct spi_nor_hwcaps {
>> #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
>> #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
>>
>> +#define SNOR_HWCAPS_4_4_4 (SNOR_HWCAPS_READ_4_4_4 | \
>> + SNOR_HWCAPS_PP_4_4_4)
>
> quad enable applies for 1-1-4 and 1-4-4 as well. How about changing
> this to:
Of course. You are right. I'm not even sure 4_4_4 falls into the
category for our quad_enable, because there's a special mode,
sometimes called qpi, for opcodes transferred in quad mode.
-michael
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next prev parent reply other threads:[~2023-12-20 8:43 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-19 10:21 [PATCH v2] mtd: spi-nor: core: Discard HW capabilities if no enable function Jaime Liao
2023-12-19 10:21 ` [PATCH v3] mtd: spi-nor: sfdp: Get the 1-1-8 and 1-8-8 protocol from SFDP Jaime Liao
2023-12-19 12:15 ` Michael Walle
2023-12-20 8:42 ` Tudor Ambarus
2023-12-20 8:51 ` Re (subset): " Tudor Ambarus
2023-12-19 12:12 ` [PATCH v2] mtd: spi-nor: core: Discard HW capabilities if no enable function Michael Walle
2023-12-20 8:07 ` Tudor Ambarus
2023-12-20 8:43 ` Michael Walle [this message]
2023-12-20 8:20 ` Tudor Ambarus
2023-12-20 8:50 ` Michael Walle
2023-12-20 8:58 ` Tudor Ambarus
2023-12-20 9:02 ` Michael Walle
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