From: Dinh Nguyen <dinguyen@kernel.org>
To: Conor Dooley <conor@kernel.org>
Cc: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Khairul Anuar Romli <khairul.anuar.romli@altera.com>,
Rob Herring <robh@kernel.org>
Subject: Re: [PATCH] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property
Date: Sun, 1 Feb 2026 13:25:55 -0600 [thread overview]
Message-ID: <aa9d982e-1a69-48b4-b9f4-16584aac9924@kernel.org> (raw)
In-Reply-To: <20260131-pasty-dicing-4ed7799aa546@spud>
On 1/31/26 14:26, Conor Dooley wrote:
> On Sat, Jan 31, 2026 at 11:26:11AM -0600, Dinh Nguyen wrote:
>> From: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>>
>> The Cadence HP NAND Flash Controller on supports DMA transactions through
>> a coherent interconnect. In previous generations SoC (Stratix10 and Agilex)
>> the interconnect was non-coherent, hence there is no need for dma-coherent
>> property to be presence. In Agilex 5, the architecture has changed. It
>> introduced a coherent interconnect that supports cache-coherent DMA.
>>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
>
> Why does this v1 have an ack?
>
I respun this patch based on the mtd tree so that the mtd maintainers
can take it. I had originally applied it to my tree, but avoid merge
conflicts, I'm going to submit it through mtd. This patch is the same as
this[1].
Sorry for any confusion.
Dinh
[1]
https://lore.kernel.org/linux-devicetree/176488419217.2206248.9983976146883123306.robh@kernel.org/
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next prev parent reply other threads:[~2026-02-01 19:26 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-31 17:26 [PATCH] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property Dinh Nguyen
2026-01-31 20:26 ` Conor Dooley
2026-02-01 19:25 ` Dinh Nguyen [this message]
2026-02-03 16:15 ` Miquel Raynal
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