Re: [PATCH v13 2/4] mtd: spi-nor: spansion: Add support for volatile QE bit

[<Tudor.Ambarus@microchip.com>]

On 4/21/22 14:36, Tudor.Ambarus@microchip.com wrote:
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> 
> On 4/21/22 13:56, Tudor.Ambarus@microchip.com wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 4/21/22 13:47, Takahiro Kuwano wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 4/21/2022 7:41 PM, Tudor.Ambarus@microchip.com wrote:
>>>> On 4/21/22 12:40, tkuw584924@gmail.com wrote:
>>> [...]
>>>>> +/**
>>>>> + * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile
>>>>> + *                                      register.
>>>>> + * @nor:       pointer to a 'struct spi_nor'
>>>>> + *
>>>>> + * It is recommended to update volatile registers in the field application due
>>>>> + * to a risk of the non-volatile registers corruption by power interrupt. This
>>>>> + * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable
>>>>> + * bit in the CFR1 non-volatile in advance (typically by a Flash programmer
>>>>> + * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is
>>>>> + * also set during Flash power-up.
>>>>> + *
>>>>> + * Return: 0 on success, -errno otherwise.
>>>>> + */
>>>>> +static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
>>>>> +{
>>>>> +       struct spi_mem_op op;
>>>>> +       u8 cfr1v_written;
>>>>> +       int ret;
>>>>> +
>>>>> +       op = (struct spi_mem_op)
>>>>> +               CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR1V,
>>>> nor->addr_width is 3, isn't it? can we use nor->addr_width instead of 3, please?
>>>>
>>> No, at the time this method is called, nor->addr_width is set to 4 by
>>> spi_nor_set_addr_width().
>>
>> I see. Allow me some time to re-read this.
> 
> Does this help you?
> https://github.com/ambarus/linux-0day/commit/05f20ab7ee349628f0e2d22a4d3852038a6c8c70

commit 05f20ab7ee349628f0e2d22a4d3852038a6c8c70
Author: Tudor Ambarus <tudor.ambarus@microchip.com>
Date:   Thu Apr 21 14:15:42 2022 +0300

    mtd: spi-nor: core: Couple the number of address bytes with the address mode
    
    Some of Infineon chips support volatile version of configuration registers
    and it is recommended to update volatile registers in the field application
    due to a risk of the non-volatile registers corruption by power interrupt.
    Such a volatile configuration register is used to enable the Quad mode.
    The register write sequence requires the number of bytes of address in
    order to be programmed. As it was before, the nor->addr_width was set to 4
    before calling the volatile Quad enable method. This was incorrect as the
    address mode was still at default (3-byte address), which resulted in
    incorrect register configuration.
    Move the setting of the number of bytes of adress after the the Quad enable
    method to allow reads or writes to registers that reguire the number of
    address bytes to work with the default address mode. Now the number of
    address bytes and the adress mode are tightly coupled, which is a natural
    change.
    Other (standard) Quad Enable methods are not affected, as they don't
    require the number of address bytes, so no functionality changes expected.
    
    Reported-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
    Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 7095bf897318..a057b177dca5 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2270,52 +2270,6 @@ static int spi_nor_default_setup(struct spi_nor *nor,
 	return 0;
 }
 
-static int spi_nor_set_addr_width(struct spi_nor *nor)
-{
-	if (nor->flags & SNOR_F_HAS_4BAIT)
-		nor->addr_width = 4;
-
-	if (nor->addr_width) {
-		/* already configured from SFDP */
-	} else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
-		/*
-		 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
-		 * in this protocol an odd address width cannot be used because
-		 * then the address phase would only span a cycle and a half.
-		 * Half a cycle would be left over. We would then have to start
-		 * the dummy phase in the middle of a cycle and so too the data
-		 * phase, and we will end the transaction with half a cycle left
-		 * over.
-		 *
-		 * Force all 8D-8D-8D flashes to use an address width of 4 to
-		 * avoid this situation.
-		 */
-		nor->addr_width = 4;
-	} else if (nor->info->addr_width) {
-		nor->addr_width = nor->info->addr_width;
-	} else {
-		nor->addr_width = 3;
-	}
-
-	if (nor->addr_width == 3 && nor->params->size > 0x1000000) {
-		/* enable 4-byte addressing if the device exceeds 16MiB */
-		nor->addr_width = 4;
-	}
-
-	if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
-		dev_dbg(nor->dev, "address width is too large: %u\n",
-			nor->addr_width);
-		return -EINVAL;
-	}
-
-	/* Set 4byte opcodes when possible. */
-	if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
-	    !(nor->flags & SNOR_F_HAS_4BAIT))
-		spi_nor_set_4byte_opcodes(nor);
-
-	return 0;
-}
-
 static int spi_nor_setup(struct spi_nor *nor,
 			 const struct spi_nor_hwcaps *hwcaps)
 {
@@ -2325,10 +2279,7 @@ static int spi_nor_setup(struct spi_nor *nor,
 		ret = nor->params->setup(nor, hwcaps);
 	else
 		ret = spi_nor_default_setup(nor, hwcaps);
-	if (ret)
-		return ret;
-
-	return spi_nor_set_addr_width(nor);
+	return ret;
 }
 
 /**
@@ -2711,6 +2662,78 @@ static int spi_nor_quad_enable(struct spi_nor *nor)
 	return nor->params->quad_enable(nor);
 }
 
+static int spi_nor_set_addr_width(struct spi_nor *nor)
+{
+	if (nor->flags & SNOR_F_HAS_4BAIT)
+		nor->addr_width = 4;
+
+	if (nor->addr_width) {
+		/* already configured from SFDP */
+	} else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
+		/*
+		 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
+		 * in this protocol an odd address width cannot be used because
+		 * then the address phase would only span a cycle and a half.
+		 * Half a cycle would be left over. We would then have to start
+		 * the dummy phase in the middle of a cycle and so too the data
+		 * phase, and we will end the transaction with half a cycle left
+		 * over.
+		 *
+		 * Force all 8D-8D-8D flashes to use an address width of 4 to
+		 * avoid this situation.
+		 */
+		nor->addr_width = 4;
+	} else if (nor->info->addr_width) {
+		nor->addr_width = nor->info->addr_width;
+	} else {
+		nor->addr_width = 3;
+	}
+
+	if (nor->addr_width == 3 && nor->params->size > 0x1000000) {
+		/* enable 4-byte addressing if the device exceeds 16MiB */
+		nor->addr_width = 4;
+	}
+
+	if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
+		dev_dbg(nor->dev, "address width is too large: %u\n",
+			nor->addr_width);
+		return -EINVAL;
+	}
+
+	/* Set 4byte opcodes when possible. */
+	if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
+	    !(nor->flags & SNOR_F_HAS_4BAIT))
+		spi_nor_set_4byte_opcodes(nor);
+
+	return 0;
+}
+
+static int spi_nor_set_addr_mode(struct spi_nor *nor)
+{
+	int ret;
+
+	ret = spi_nor_set_addr_width(nor);
+	if (ret)
+		return ret;
+
+	if (nor->addr_width == 4 &&
+	    nor->read_proto != SNOR_PROTO_8_8_8_DTR &&
+	    !(nor->flags & SNOR_F_4B_OPCODES)) {
+		/*
+		 * If the RESET# pin isn't hooked up properly, or the system
+		 * otherwise doesn't perform a reset command in the boot
+		 * sequence, it's impossible to 100% protect against unexpected
+		 * reboots (e.g., crashes). Warn the user (or hopefully, system
+		 * designer) that this is bad.
+		 */
+		WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
+			  "enabling reset hack; may not recover from unexpected reboots\n");
+		nor->params->set_4byte_addr_mode(nor, true);
+	}
+
+	return 0;
+}
+
 static int spi_nor_init(struct spi_nor *nor)
 {
 	int err;
@@ -2742,22 +2765,7 @@ static int spi_nor_init(struct spi_nor *nor)
 	     nor->flags & SNOR_F_SWP_IS_VOLATILE))
 		spi_nor_try_unlock_all(nor);
 
-	if (nor->addr_width == 4 &&
-	    nor->read_proto != SNOR_PROTO_8_8_8_DTR &&
-	    !(nor->flags & SNOR_F_4B_OPCODES)) {
-		/*
-		 * If the RESET# pin isn't hooked up properly, or the system
-		 * otherwise doesn't perform a reset command in the boot
-		 * sequence, it's impossible to 100% protect against unexpected
-		 * reboots (e.g., crashes). Warn the user (or hopefully, system
-		 * designer) that this is bad.
-		 */
-		WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
-			  "enabling reset hack; may not recover from unexpected reboots\n");
-		nor->params->set_4byte_addr_mode(nor, true);
-	}
-
-	return 0;
+	return spi_nor_set_addr_mode(nor);
 }


> 
> Find the entire branch at:
> https://github.com/ambarus/linux-0day/commits/spi-nor/next
> 
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