From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de ([2001:470:1f0b:1c35:abcd:42:0:1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SCpXe-0004y9-QG for linux-mtd@lists.infradead.org; Wed, 28 Mar 2012 09:51:48 +0000 Date: Wed, 28 Mar 2012 11:51:42 +0200 (CEST) From: Thomas Gleixner To: Brian Norris Subject: Re: nand_base - kill chip->oob_poi? In-Reply-To: Message-ID: References: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Cc: linux-mtd@lists.infradead.org, David Woodhouse , Artem Bityutskiy List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, 27 Mar 2012, Brian Norris wrote: > Hi, > > I'm looking to support a new NAND hardware controller, and it doesn't > support OOB read/write for its fastest modes of operation, since most > normal activity (i.e., UBI(FS)) doesn't need OOB. So I'm trying to And how is ECC working for that "normal" activity ? Using NAND w/o ECC is doomed for fail. Aside of that improvements to the NAND code are always welcome, modifications which are solely done to support insane usage of NAND FLASH not so much. Thanks, tglx