Re: [PATCH v2] mtd: spinand: Add support for AllianceMemory AS5F34G04SND

[Mario Kicherer <dev@kicherer.org>]

On 2023-01-25 15:27, Miquel Raynal wrote:
>> >> +static int am_ecc_get_status(struct spinand_device *spinand, u8 >> status)
>> >> +{
>> >> +	switch (status & AM_STATUS_ECC_BITMASK) {
>> >> +	case AM_STATUS_ECC_NONE_DETECTED:
>> >> +		return 0;
>> >> +
>> >> +	case AM_STATUS_ECC_1_CORRECTED:
>> >> +		return 1;
>> >> +
>> >> +	case AM_STATUS_ECC_MAX_CORRECTED:
>> >> +		return 8;
>> >> +
>> >> +	case AM_STATUS_ECC_1_DETECTED:
>> >
>> > What does this mean "1 detected"?
>> 
>> According to the manual, the chip can report that a bit error was 
>> detected
>> but could not be corrected.
> 
> That does not make a lot of sense. Either you use a Hamming algorithm,
> you will be able to correct 1 bit error and to detect 2 bit errors, or
> you use another algorithm (BCH, usually) with a strength of X (X > 1)
> and you'll be able to correct up to X errors and detect X+1 errors.
> 
> But only being able to detect a single bit flip without being able to
> correct it is strange (even useless?). So I don't understand how it
> should be used.

Unfortunately, I do not have much experience with NAND flashes. The
manual does not say much more - page 41 in [1] in case you want to
see for yourself. I thought returning -EBADMSG in this case would be
the right thing to do as an uncorrectable error happened.

I have not used the flash much yet, so I cannot say that I have much
confidence into the chip's error reporting. So far the flash worked
without issues.

Should I change something in the patch?

Best regards,
Mario

[1] 
https://www.alliancememory.com/wp-content/uploads/pdf/flash/AllianceMemory_SPI_NAND_Flash_July2020_Rev1.0.pdf

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