From: Takahiro Kuwano <tkuw584924@gmail.com>
To: Tudor.Ambarus@microchip.com, Takahiro.Kuwano@infineon.com,
juliensu@mxic.com.tw, jaimeliao@mxic.com.tw,
Bacem.Daassi@infineon.com, beanhuo@micron.com,
shiva.linuxworks@gmail.com, sshivamurthy@micron.com
Cc: michael@walle.cc, p.yadav@ti.com, linux-mtd@lists.infradead.org
Subject: Re: How does an SPI NOR handle a single byte write in Octal DTR mode?
Date: Mon, 20 Dec 2021 19:32:07 +0900 [thread overview]
Message-ID: <d40c879c-c419-82c4-c385-0a03e105a622@gmail.com> (raw)
In-Reply-To: <f593ded7-6cb1-7645-a0b4-dc20b5576d1d@microchip.com>
Hi Tudor,
In case of Infineon(Cypress) S28 devices, it can be done by de-asserting
chip select before clock falling (not sure typical controllers support this).
That means the device can take odd address in 8D-8D-8D mode.
Thanks,
Takahiro
On 12/20/2021 6:36 PM, Tudor.Ambarus@microchip.com wrote:
> Hello,
>
> We're trying to understand how flashes handle single byte writes in
> Octal DTR mode, and since we haven't found this info in the datasheets
> that we read, you're our only hope. Can you shed some light and let us
> now:
> 1/ Do the flashes ignore the second byte in Octal DTR mode? Are we forced
> to first read the byte that we want to update together with the second byte,
> so that when writing in Octal DTR mode to write the 2nd byte that we've just
> read, so that we don't change its value?
> 2/ Can reads or writes start at an odd address in 8D-8D-8D mode? Pratyush
> proposed something at:
> https://patchwork.ozlabs.org/project/linux-mtd/list/?series=246518
> Are the assumptions correct in the patch set?
>
> Feel free to forward this to anyone interested. Thanks.
> ta
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>
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next prev parent reply other threads:[~2021-12-20 10:33 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-20 9:36 How does an SPI NOR handle a single byte write in Octal DTR mode? Tudor.Ambarus
2021-12-20 10:32 ` Takahiro Kuwano [this message]
2021-12-20 15:47 ` Michael Walle
2021-12-21 23:32 ` Takahiro Kuwano
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