[PATCH v3 0/5] mtd: spi-nor: introduce die erase

[PATCH v3 0/5] mtd: spi-nor: introduce die erase

[Tudor Ambarus]

changes in v3:
- fix code, thanks to Fabio's testing
- found a n25q00 and tested on my side too
- fixed micron's die erase support

Add support for die erase.
JESD216 mentions die erase, but does not provide an opcode for it.
Check BFPT dword 11, bits 30:24, "Chip Erase, Typical time", it says:

"Typical time to erase one chip (die). User must poll device busy to
determine if the operation has completed. For a device consisting of
multiple dies, that are individually accessed, the time is for each die
to which a chip erase command is applied."

So when a flash consists of a single die, this is the erase time for the
full chip (die) erase, and when it consists of multiple dies, it's the
die erase time. Chip and die are the same thing.

For what concerns the Micron flashes, unfortunately Micron does not
provide a 4-byte opcode equivalent for the die erase. The SFDP 4BAIT
table fails to consider the die erase too, the standard can be improved.
Thus we're forced to enter in the 4 byte address mode in order to benefit
of the die erase. This comes with some changes into the core.
    
Tested on n25q00. This flash defines the 4BAIT SFDP table, thus it will
use the 4BAIT opcodes for reads, page programs or erases, with the
exception that it will use the die erase command in the 4 byte address
mode. 

Fabio Estevam (1):
  mtd: spi-nor: micron-st: Add support for mt25qu01g

Tudor Ambarus (4):
  mtd: spi-nor: add erase die (chip) capability
  mtd: spi-nor: spansion: enable die erase for multi die flashes
  mtd: spi-nor: micron-st: enable die erase for multi die flashes
  mtd: spi-nor: remove NO_CHIP_ERASE flag

 drivers/mtd/spi-nor/core.c      | 143 ++++++++++++++++++++------------
 drivers/mtd/spi-nor/core.h      |  16 ++--
 drivers/mtd/spi-nor/debugfs.c   |   2 +-
 drivers/mtd/spi-nor/micron-st.c |  59 ++++++++++++-
 drivers/mtd/spi-nor/spansion.c  |   4 +-
 5 files changed, 158 insertions(+), 66 deletions(-)

-- 
2.34.1


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[PATCH v3 1/5] mtd: spi-nor: add erase die (chip) capability

[Tudor Ambarus]

JESD216 mentions die erase, but does not provide an opcode for it.
Check BFPT dword 11, bits 30:24, "Chip Erase, Typical time", it says:

"Typical time to erase one chip (die). User must poll device busy to
determine if the operation has completed. For a device consisting of
multiple dies, that are individually accessed, the time is for each die
to which a chip erase command is applied."

So when a flash consists of a single die, this is the erase time for the
full chip (die) erase, and when it consists of multiple dies, it's the
die erase time. Chip and die are the same thing.

Add support for die erase. For now, benefit of the die erase when addr
and len are aligned with die size. This could be improved however for
the uniform and non-uniform erases cases to use the die erase when
possible. For example if one requests that an erase of a 2 die device
starting from the last 64KB of the first die to the end of the flash
size, we could use just 2 commands, a 64KB erase and a die erase.
This improvement is left as an exercise for the reader.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 drivers/mtd/spi-nor/core.c    | 108 +++++++++++++++++++++++-----------
 drivers/mtd/spi-nor/core.h    |   8 ++-
 drivers/mtd/spi-nor/debugfs.c |   2 +-
 3 files changed, 81 insertions(+), 37 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 25a64c65717d..479494cf00c9 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -1060,24 +1060,32 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
 }
 
 /**
- * spi_nor_erase_chip() - Erase the entire flash memory.
+ * spi_nor_erase_die() - Erase the entire die.
  * @nor:	pointer to 'struct spi_nor'.
+ * @addr:	address of the die.
+ * @die_size:	size of the die.
  *
  * Return: 0 on success, -errno otherwise.
  */
-static int spi_nor_erase_chip(struct spi_nor *nor)
+static int spi_nor_erase_die(struct spi_nor *nor, loff_t addr, size_t die_size)
 {
+	bool multi_die = nor->mtd.size != die_size;
 	int ret;
 
-	dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
+	dev_dbg(nor->dev, " %lldKiB\n", (long long)(die_size >> 10));
 
 	if (nor->spimem) {
-		struct spi_mem_op op = SPI_NOR_CHIP_ERASE_OP;
+		struct spi_mem_op op =
+			SPI_NOR_DIE_ERASE_OP(nor->params->die_erase_opcode,
+					     nor->addr_nbytes, addr, multi_die);
 
 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 
 		ret = spi_mem_exec_op(nor->spimem, &op);
 	} else {
+		if (multi_die)
+			return -EOPNOTSUPP;
+
 		ret = spi_nor_controller_ops_write_reg(nor,
 						       SPINOR_OP_CHIP_ERASE,
 						       NULL, 0);
@@ -1792,6 +1800,51 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
 	return ret;
 }
 
+static int spi_nor_erase_dice(struct spi_nor *nor, loff_t addr,
+			      size_t len, size_t die_size)
+{
+	unsigned long timeout;
+	int ret;
+
+	/*
+	 * Scale the timeout linearly with the size of the flash, with
+	 * a minimum calibrated to an old 2MB flash. We could try to
+	 * pull these from CFI/SFDP, but these values should be good
+	 * enough for now.
+	 */
+	timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
+		      CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
+		      (unsigned long)(nor->mtd.size / SZ_2M));
+
+	do {
+		ret = spi_nor_lock_device(nor);
+		if (ret)
+			return ret;
+
+		ret = spi_nor_write_enable(nor);
+		if (ret) {
+			spi_nor_unlock_device(nor);
+			return ret;
+		}
+
+		ret = spi_nor_erase_die(nor, addr, die_size);
+
+		spi_nor_unlock_device(nor);
+		if (ret)
+			return ret;
+
+		ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
+		if (ret)
+			return ret;
+
+		addr += die_size;
+		len -= die_size;
+
+	} while (len);
+
+	return 0;
+}
+
 /*
  * Erase an address range on the nor chip.  The address range may extend
  * one or more erase sectors. Return an error if there is a problem erasing.
@@ -1799,7 +1852,10 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
+	u8 n_dice = nor->params->n_dice;
+	bool multi_die_erase = false;
 	u32 addr, len, rem;
+	size_t die_size;
 	int ret;
 
 	dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
@@ -1814,39 +1870,22 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
 	addr = instr->addr;
 	len = instr->len;
 
+	if (n_dice) {
+		die_size = div_u64(mtd->size, n_dice);
+		if (!(len & (die_size - 1)) && !(addr & (die_size - 1)))
+			multi_die_erase = true;
+	} else {
+		die_size = mtd->size;
+	}
+
 	ret = spi_nor_prep_and_lock_pe(nor, instr->addr, instr->len);
 	if (ret)
 		return ret;
 
-	/* whole-chip erase? */
-	if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
-		unsigned long timeout;
-
-		ret = spi_nor_lock_device(nor);
-		if (ret)
-			goto erase_err;
-
-		ret = spi_nor_write_enable(nor);
-		if (ret) {
-			spi_nor_unlock_device(nor);
-			goto erase_err;
-		}
-
-		ret = spi_nor_erase_chip(nor);
-		spi_nor_unlock_device(nor);
-		if (ret)
-			goto erase_err;
-
-		/*
-		 * Scale the timeout linearly with the size of the flash, with
-		 * a minimum calibrated to an old 2MB flash. We could try to
-		 * pull these from CFI/SFDP, but these values should be good
-		 * enough for now.
-		 */
-		timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
-			      CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
-			      (unsigned long)(mtd->size / SZ_2M));
-		ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
+	/* chip (die) erase? */
+	if ((len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) ||
+	    multi_die_erase) {
+		ret = spi_nor_erase_dice(nor, addr, len, die_size);
 		if (ret)
 			goto erase_err;
 
@@ -2902,6 +2941,9 @@ static int spi_nor_late_init_params(struct spi_nor *nor)
 			return ret;
 	}
 
+	if (!nor->params->die_erase_opcode)
+		nor->params->die_erase_opcode = SPINOR_OP_CHIP_ERASE;
+
 	/* Default method kept for backward compatibility. */
 	if (!params->set_4byte_addr_mode)
 		params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index a456042379ee..b43ea2d49e74 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -85,9 +85,9 @@
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_NO_DATA)
 
-#define SPI_NOR_CHIP_ERASE_OP						\
-	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0),		\
-		   SPI_MEM_OP_NO_ADDR,					\
+#define SPI_NOR_DIE_ERASE_OP(opcode, addr_nbytes, addr, dice)		\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0),				\
+		   SPI_MEM_OP_ADDR(dice ? addr_nbytes : 0, addr, 0),	\
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_NO_DATA)
 
@@ -362,6 +362,7 @@ struct spi_nor_otp {
  *			command in octal DTR mode.
  * @n_banks:		number of banks.
  * @n_dice:		number of dice in the flash memory.
+ * @die_erase_opcode:	die erase opcode. Defaults to SPINOR_OP_CHIP_ERASE.
  * @vreg_offset:	volatile register offset for each die.
  * @hwcaps:		describes the read and page program hardware
  *			capabilities.
@@ -399,6 +400,7 @@ struct spi_nor_flash_parameter {
 	u8				rdsr_addr_nbytes;
 	u8				n_banks;
 	u8				n_dice;
+	u8				die_erase_opcode;
 	u32				*vreg_offset;
 
 	struct spi_nor_hwcaps		hwcaps;
diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
index 6e163cb5b478..2dbda6b6938a 100644
--- a/drivers/mtd/spi-nor/debugfs.c
+++ b/drivers/mtd/spi-nor/debugfs.c
@@ -138,7 +138,7 @@ static int spi_nor_params_show(struct seq_file *s, void *data)
 
 	if (!(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
 		string_get_size(params->size, 1, STRING_UNITS_2, buf, sizeof(buf));
-		seq_printf(s, " %02x (%s)\n", SPINOR_OP_CHIP_ERASE, buf);
+		seq_printf(s, " %02x (%s)\n", nor->params->die_erase_opcode, buf);
 	}
 
 	seq_puts(s, "\nsector map\n");
-- 
2.34.1


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[PATCH v3 2/5] mtd: spi-nor: spansion: enable die erase for multi die flashes

[Tudor Ambarus]

Enable die erase for spansion multi die flashes.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Tested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
---
 drivers/mtd/spi-nor/spansion.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 12921344373d..6cc237c24e07 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -17,6 +17,7 @@
 
 #define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */
 #define SPINOR_OP_CLPEF		0x82	/* Clear program/erase failure flags */
+#define SPINOR_OP_CYPRESS_DIE_ERASE		0x61	/* Chip (die) erase */
 #define SPINOR_OP_RD_ANY_REG			0x65	/* Read any register */
 #define SPINOR_OP_WR_ANY_REG			0x71	/* Write any register */
 #define SPINOR_REG_CYPRESS_VREG			0x00800000
@@ -644,6 +645,7 @@ static int s25hx_t_late_init(struct spi_nor *nor)
 	params->ready = cypress_nor_sr_ready_and_clear;
 	cypress_nor_ecc_init(nor);
 
+	params->die_erase_opcode = SPINOR_OP_CYPRESS_DIE_ERASE;
 	return 0;
 }
 
@@ -933,7 +935,6 @@ static const struct flash_info spansion_nor_parts[] = {
 		.id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90),
 		.name = "s25hl02gt",
 		.mfr_flags = USE_CLPEF,
-		.flags = NO_CHIP_ERASE,
 		.fixups = &s25hx_t_fixups
 	}, {
 		.id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90),
@@ -954,7 +955,6 @@ static const struct flash_info spansion_nor_parts[] = {
 		.id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90),
 		.name = "s25hs02gt",
 		.mfr_flags = USE_CLPEF,
-		.flags = NO_CHIP_ERASE,
 		.fixups = &s25hx_t_fixups
 	}, {
 		.id = SNOR_ID(0x34, 0x5a, 0x1a),
-- 
2.34.1


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[PATCH v3 3/5] mtd: spi-nor: micron-st: enable die erase for multi die flashes

[Tudor Ambarus]

Enable die erase for multi die flashes, it will speed the erase time.

Unfortunately, Micron does not provide a 4-byte opcode equivalent for
the die erase. The SFDP 4BAIT table fails to consider the die erase too,
the standard can be improved. Thus we're forced to enter in the 4 byte
address mode in order to benefit of the die erase.

Tested on n25q00. This flash defines the 4BAIT SFDP table, thus it will
use the 4BAIT opcodes for reads, page programs or erases, with the
exception that it will use the die erase command in the 4 byte address
mode.

Link: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_1gb_3v_65nm.pdf?rev=b6eba74759984f749f8c039bc5bc47b7
Link: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_l_02g_cbb_0.pdf?rev=43f7f66fc8da4d7d901b35fa51284c8f
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---

Tested on sama5d2_xplained using the "atmel,sama5d2-qspi" spi controller
and by operating the flash at 80MHz.

root@sama5d2-xplained-emmc:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/partname
n25q00
root@sama5d2-xplained-emmc:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/jedec_id 
20ba21
root@sama5d2-xplained-emmc:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/manufacturer 
st
root@sama5d2-xplained-emmc:~# xxd -p /sys/bus/spi/devices/spi1.0/spi-nor/sfdp         
53464450060101ff00060110300000ff84000102800000ffffffffffffff
ffffffffffffffffffffffffffffffffffffe520fbffffffff3f29eb276b
273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e
03e1ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff
ffffffffffffffffffe7ffff21dcffff
root@sama5d2-xplained-emmc:~# sha256sum /sys/bus/spi/devices/spi1.0/spi-nor/sfdp
e49dfee6eeb73c55e94c07a8c7d352dd7d8774b830a64ed1059ef6e7bc833668  /sys/bus/spi/devices/spi1.0/spi-nor/sfdp

root@sama5d2-xplained-emmc:~# cat /sys/kernel/debug/spi-nor/spi1.0/capabilities
Supported read modes by the flash
 1S-1S-1S
  opcode	0x13
  mode cycles	0
  dummy cycles	0
 1S-1S-1S (fast read)
  opcode	0x0c
  mode cycles	0
  dummy cycles	8
 1S-1S-2S
  opcode	0x3c
  mode cycles	1
  dummy cycles	7
 1S-2S-2S
  opcode	0xbc
  mode cycles	1
  dummy cycles	7
 2S-2S-2S
  opcode	0xbc
  mode cycles	1
  dummy cycles	7
 1S-1S-4S
  opcode	0x6c
  mode cycles	1
  dummy cycles	7
 1S-4S-4S
  opcode	0xec
  mode cycles	1
  dummy cycles	9
 4S-4S-4S
  opcode	0xec
  mode cycles	1
  dummy cycles	9

Supported page program modes by the flash
 1S-1S-1S
  opcode	0x12
 1S-1S-4S
  opcode	0x34
 1S-4S-4S
  opcode	0x3e

 root@sama5d2-xplained-emmc:~# cat /sys/kernel/debug/spi-nor/spi1.0/params
name		n25q00
id		20 ba 21 10 40 00
size		128 MiB
write size	1
page size	256
address nbytes	4
flags		HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_4BIT_BP | HAS_SR_BP3_BIT6 | SOFT_RESET

opcodes
 read		0xec
  dummy cycles	10
 erase		0x21
 program	0x3e
 8D extension	none

protocols
 read		1S-4S-4S
 write		1S-4S-4S
 register	1S-1S-1S

erase commands
 21 (4.00 KiB) [1]
 dc (64.0 KiB) [3]
 c4 (128 MiB)

sector map
 region (in hex)   | erase mask | flags
 ------------------+------------+----------
 00000000-07ffffff |     [ 123] | 
 
root@sama5d2-xplained-emmc:~# dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.1 MB, 2.0 MiB) copied, 1.40662 s, 1.5 MB/s
root@sama5d2-xplained-emmc:~# mtd_debug erase /dev/mtd1 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
root@sama5d2-xplained-emmc:~# hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
root@sama5d2-xplained-emmc:~# sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5  spi_read
root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
root@sama5d2-xplained-emmc:~# sha256sum spi*
15608dfc2a8ef8352c1ec18863592002d8bb54195f0163794ac78c8599496808  spi_read
15608dfc2a8ef8352c1ec18863592002d8bb54195f0163794ac78c8599496808  spi_test
root@sama5d2-xplained-emmc:~# mtd_debug erase /dev/mtd1 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
root@sama5d2-xplained-emmc:~# sha256sum spi*
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5  spi_read
15608dfc2a8ef8352c1ec18863592002d8bb54195f0163794ac78c8599496808  spi_test

root@sama5d2-xplained-emmc:~# mtd_debug info /dev/mtd1
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 134217728 (128M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1 
mtd.oobsize = 0 
regions = 0

root@sama5d2-xplained-emmc:~# time mtd_debug erase /dev/mtd1 0 134217728
Erased 134217728 bytes from address 0x00000000 in flash

real	0m6.900s
user	0m0.000s
sys	0m6.899s

root@sama5d2-xplained-emmc:~# echo "ta writes something into the first die" > firstdie
root@sama5d2-xplained-emmc:~# echo "ta writes something into the second die" > seconddie
root@sama5d2-xplained-emmc:~# echo "ta writes something into the 3rd die 33333" > thirddie
root@sama5d2-xplained-emmc:~# echo "ta writes something into the 4th die 444444" > fourthdie

root@sama5d2-xplained-emmc:~# ls -al
total 176168
drwx------ 3 root root      4096 Apr 29 00:48 .
drwxr-xr-x 3 root root      4096 Mar  9  2018 ..
-rw-r--r-- 1 root root        39 Apr 29 00:45 firstdie
-rw-r--r-- 1 root root        44 Apr 29 00:48 fourthdie
-rw-r--r-- 1 root root        40 Apr 29 00:45 seconddie
-rw-r--r-- 1 root root   2097152 Apr 29 00:42 spi_read
-rw-r--r-- 1 root root   2097152 Apr 29 00:40 spi_test
-rw-r--r-- 1 root root        43 Apr 29 00:47 thirddie

root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 0 39 firstdie
Copied 39 bytes from firstdie to address 0x00000000 in flash
root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 33554432 40 seconddie 
Copied 40 bytes from seconddie to address 0x02000000 in flash
root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 67108864 43 thirddie 
Copied 43 bytes from thirddie to address 0x04000000 in flash
root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 100663296 44 fourthdie 
Copied 44 bytes from fourthdie to address 0x06000000 in flash
root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 0 134217728 read
Copied 134217728 bytes from address 0x00000000 in flash to read
root@sama5d2-xplained-emmc:~# hexdump -C read
00000000  74 61 20 77 72 69 74 65  73 20 73 6f 6d 65 74 68  |ta writes someth|
00000010  69 6e 67 20 69 6e 74 6f  20 74 68 65 20 66 69 72  |ing into the fir|
00000020  73 74 20 64 69 65 0a ff  ff ff ff ff ff ff ff ff  |st die..........|
00000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
*
02000000  74 61 20 77 72 69 74 65  73 20 73 6f 6d 65 74 68  |ta writes someth|
02000010  69 6e 67 20 69 6e 74 6f  20 74 68 65 20 73 65 63  |ing into the sec|
02000020  6f 6e 64 20 64 69 65 0a  ff ff ff ff ff ff ff ff  |ond die.........|
02000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
*
04000000  74 61 20 77 72 69 74 65  73 20 73 6f 6d 65 74 68  |ta writes someth|
04000010  69 6e 67 20 69 6e 74 6f  20 74 68 65 20 33 72 64  |ing into the 3rd|
04000020  20 64 69 65 20 33 33 33  33 33 0a ff ff ff ff ff  | die 33333......|
04000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
*
06000000  74 61 20 77 72 69 74 65  73 20 73 6f 6d 65 74 68  |ta writes someth|
06000010  69 6e 67 20 69 6e 74 6f  20 74 68 65 20 34 74 68  |ing into the 4th|
06000020  20 64 69 65 20 34 34 34  34 34 34 0a ff ff ff ff  | die 444444.....|
06000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
*
08000000

root@sama5d2-xplained-emmc:~# time mtd_debug erase /dev/mtd1 0 134217728
Erased 134217728 bytes from address 0x00000000 in flash

real	0m3.800s
user	0m0.001s
sys	0m3.751s
root@sama5d2-xplained-emmc:~# echo "ta writes a something crossing the dice" > cross-dice
root@sama5d2-xplained-emmc:~# ls -al
total 176172
drwx------ 3 root root      4096 Apr 29 00:54 .
drwxr-xr-x 3 root root      4096 Mar  9  2018 ..
-rw-r--r-- 1 root root        40 Apr 29 00:54 cross-dice

root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 67108857 40 cross-dice 
Copied 40 bytes from cross-dice to address 0x03fffff9 in flash
root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 0 134217728 read
Copied 134217728 bytes from address 0x00000000 in flash to read
root@sama5d2-xplained-emmc:~# hexdump -C read
00000000  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
*
03fffff0  ff ff ff ff ff ff ff ff  ff 74 61 20 77 72 69 74  |.........ta writ|
04000000  65 73 20 61 20 73 6f 6d  65 74 68 69 6e 67 20 63  |es a something c|
04000010  72 6f 73 73 69 6e 67 20  74 68 65 20 64 69 63 65  |rossing the dice|
04000020  0a ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
04000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
*
08000000
root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 67108857 40 read       
Copied 40 bytes from address 0x03fffff9 in flash to read
root@sama5d2-xplained-emmc:~# hexdump -C read
00000000  74 61 20 77 72 69 74 65  73 20 61 20 73 6f 6d 65  |ta writes a some|
00000010  74 68 69 6e 67 20 63 72  6f 73 73 69 6e 67 20 74  |thing crossing t|
00000020  68 65 20 64 69 63 65 0a                           |he dice.|
00000028
root@sama5d2-xplained-emmc:~# 

 drivers/mtd/spi-nor/core.c      | 32 ++++++++++++++++---------------
 drivers/mtd/spi-nor/micron-st.c | 34 +++++++++++++++++++++++++++++----
 2 files changed, 47 insertions(+), 19 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 479494cf00c9..52e5b569ddfd 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2935,6 +2935,9 @@ static int spi_nor_late_init_params(struct spi_nor *nor)
 			return ret;
 	}
 
+	/* Needed by some flashes late_init hooks. */
+	spi_nor_init_flags(nor);
+
 	if (nor->info->fixups && nor->info->fixups->late_init) {
 		ret = nor->info->fixups->late_init(nor);
 		if (ret)
@@ -2948,7 +2951,6 @@ static int spi_nor_late_init_params(struct spi_nor *nor)
 	if (!params->set_4byte_addr_mode)
 		params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;
 
-	spi_nor_init_flags(nor);
 	spi_nor_init_fixup_flags(nor);
 
 	/*
@@ -3186,6 +3188,18 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
 	struct spi_nor_flash_parameter *params = nor->params;
 	int ret;
 
+	if (enable) {
+		/*
+		 * If the RESET# pin isn't hooked up properly, or the system
+		 * otherwise doesn't perform a reset command in the boot
+		 * sequence, it's impossible to 100% protect against unexpected
+		 * reboots (e.g., crashes). Warn the user (or hopefully, system
+		 * designer) that this is bad.
+		 */
+		WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
+			  "enabling reset hack; may not recover from unexpected reboots\n");
+	}
+
 	ret = params->set_4byte_addr_mode(nor, enable);
 	if (ret && ret != -ENOTSUPP)
 		return ret;
@@ -3234,20 +3248,8 @@ static int spi_nor_init(struct spi_nor *nor)
 
 	if (nor->addr_nbytes == 4 &&
 	    nor->read_proto != SNOR_PROTO_8_8_8_DTR &&
-	    !(nor->flags & SNOR_F_4B_OPCODES)) {
-		/*
-		 * If the RESET# pin isn't hooked up properly, or the system
-		 * otherwise doesn't perform a reset command in the boot
-		 * sequence, it's impossible to 100% protect against unexpected
-		 * reboots (e.g., crashes). Warn the user (or hopefully, system
-		 * designer) that this is bad.
-		 */
-		WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
-			  "enabling reset hack; may not recover from unexpected reboots\n");
-		err = spi_nor_set_4byte_addr_mode(nor, true);
-		if (err)
-			return err;
-	}
+	    !(nor->flags & SNOR_F_4B_OPCODES))
+		return spi_nor_set_4byte_addr_mode(nor, true);
 
 	return 0;
 }
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 8920547c12bf..b63f1e9b97d0 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -11,6 +11,7 @@
 /* flash_info mfr_flag. Used to read proprietary FSR register. */
 #define USE_FSR		BIT(0)
 
+#define SPINOR_OP_MT_DIE_ERASE	0xc4	/* Chip (die) erase opcode */
 #define SPINOR_OP_RDFSR		0x70	/* Read flag status register */
 #define SPINOR_OP_CLFSR		0x50	/* Clear flag status register */
 #define SPINOR_OP_MT_DTR_RD	0xfd	/* Fast Read opcode in DTR mode */
@@ -192,6 +193,30 @@ static struct spi_nor_fixups mt25qu512a_fixups = {
 	.post_bfpt = mt25qu512a_post_bfpt_fixup,
 };
 
+static int st_nor_four_die_late_init(struct spi_nor *nor)
+{
+	struct spi_nor_flash_parameter *params = nor->params;
+
+	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+	params->n_dice = 4;
+
+	/*
+	 * Unfortunately the die erase opcode does not have a 4-byte opcode
+	 * correspondent for these flashes. The SFDP 4BAIT table fails to
+	 * consider the die erase too. We're forced to enter in the 4 byte
+	 * address mode in order to benefit of the die erase.
+	 */
+	return spi_nor_set_4byte_addr_mode(nor, true);
+}
+
+static struct spi_nor_fixups n25q00_fixups = {
+	.late_init = st_nor_four_die_late_init,
+};
+
+static struct spi_nor_fixups mt25q02_fixups = {
+	.late_init = st_nor_four_die_late_init,
+};
+
 static const struct flash_info st_nor_parts[] = {
 	{
 		.name = "m25p05-nonjedec",
@@ -366,16 +391,17 @@ static const struct flash_info st_nor_parts[] = {
 		.name = "n25q00",
 		.size = SZ_128M,
 		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
-			 SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE,
+			 SPI_NOR_BP3_SR_BIT6,
 		.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
 		.mfr_flags = USE_FSR,
+		.fixups = &n25q00_fixups,
 	}, {
 		.id = SNOR_ID(0x20, 0xba, 0x22),
 		.name = "mt25ql02g",
 		.size = SZ_256M,
-		.flags = NO_CHIP_ERASE,
 		.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
 		.mfr_flags = USE_FSR,
+		.fixups = &mt25q02_fixups,
 	}, {
 		.id = SNOR_ID(0x20, 0xbb, 0x15),
 		.name = "n25q016a",
@@ -433,16 +459,16 @@ static const struct flash_info st_nor_parts[] = {
 		.id = SNOR_ID(0x20, 0xbb, 0x21),
 		.name = "n25q00a",
 		.size = SZ_128M,
-		.flags = NO_CHIP_ERASE,
 		.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
 		.mfr_flags = USE_FSR,
+		.fixups = &n25q00_fixups,
 	}, {
 		.id = SNOR_ID(0x20, 0xbb, 0x22),
 		.name = "mt25qu02g",
 		.size = SZ_256M,
-		.flags = NO_CHIP_ERASE,
 		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
 		.mfr_flags = USE_FSR,
+		.fixups = &mt25q02_fixups,
 	}
 };
 
-- 
2.34.1


______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v3 4/5] mtd: spi-nor: remove NO_CHIP_ERASE flag

[Tudor Ambarus]

There's no flash using it and we'd like to rely instead on SFDP data,
thus remove it.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 drivers/mtd/spi-nor/core.c | 3 ---
 drivers/mtd/spi-nor/core.h | 8 +++-----
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 52e5b569ddfd..503fed90c2fa 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2888,9 +2888,6 @@ static void spi_nor_init_flags(struct spi_nor *nor)
 			nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
 	}
 
-	if (flags & NO_CHIP_ERASE)
-		nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
-
 	if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 &&
 	    !nor->controller_ops)
 		nor->flags |= SNOR_F_RWW;
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index b43ea2d49e74..29ed67725b18 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -489,7 +489,6 @@ struct spi_nor_id {
  *                            Usually these will power-up in a write-protected
  *                            state.
  *   SPI_NOR_NO_ERASE:        no erase command needed.
- *   NO_CHIP_ERASE:           chip does not support chip erase.
  *   SPI_NOR_NO_FR:           can't do fastread.
  *   SPI_NOR_QUAD_PP:         flash supports Quad Input Page Program.
  *   SPI_NOR_RWW:             flash supports reads while write.
@@ -539,10 +538,9 @@ struct flash_info {
 #define SPI_NOR_BP3_SR_BIT6		BIT(4)
 #define SPI_NOR_SWP_IS_VOLATILE		BIT(5)
 #define SPI_NOR_NO_ERASE		BIT(6)
-#define NO_CHIP_ERASE			BIT(7)
-#define SPI_NOR_NO_FR			BIT(8)
-#define SPI_NOR_QUAD_PP			BIT(9)
-#define SPI_NOR_RWW			BIT(10)
+#define SPI_NOR_NO_FR			BIT(7)
+#define SPI_NOR_QUAD_PP			BIT(8)
+#define SPI_NOR_RWW			BIT(9)
 
 	u8 no_sfdp_flags;
 #define SPI_NOR_SKIP_SFDP		BIT(0)
-- 
2.34.1


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[PATCH v3 5/5] mtd: spi-nor: micron-st: Add support for mt25qu01g

[Tudor Ambarus]

From: Fabio Estevam <festevam@denx.de>

Add support for the MT25QU01G 128MB Micron Serial NOR Flash Memory
model.

Link: https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_01g_bbb_0.pdf
Signed-off-by: Fabio Estevam <festevam@denx.de>
[ta: introduce die erase]
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 drivers/mtd/spi-nor/micron-st.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index b63f1e9b97d0..3c6499fdb712 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -209,10 +209,30 @@ static int st_nor_four_die_late_init(struct spi_nor *nor)
 	return spi_nor_set_4byte_addr_mode(nor, true);
 }
 
+static int st_nor_two_die_late_init(struct spi_nor *nor)
+{
+	struct spi_nor_flash_parameter *params = nor->params;
+
+	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+	params->n_dice = 2;
+
+	/*
+	 * Unfortunately the die erase opcode does not have a 4-byte opcode
+	 * correspondent for these flashes. The SFDP 4BAIT table fails to
+	 * consider the die erase too. We're forced to enter in the 4 byte
+	 * address mode in order to benefit of the die erase.
+	 */
+	return spi_nor_set_4byte_addr_mode(nor, true);
+}
+
 static struct spi_nor_fixups n25q00_fixups = {
 	.late_init = st_nor_four_die_late_init,
 };
 
+static struct spi_nor_fixups mt25q01_fixups = {
+	.late_init = st_nor_two_die_late_init,
+};
+
 static struct spi_nor_fixups mt25q02_fixups = {
 	.late_init = st_nor_four_die_late_init,
 };
@@ -455,6 +475,11 @@ static const struct flash_info st_nor_parts[] = {
 			 SPI_NOR_BP3_SR_BIT6,
 		.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
 		.mfr_flags = USE_FSR,
+	}, {
+		.id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00),
+		.name = "mt25qu01g",
+		.mfr_flags = USE_FSR,
+		.fixups = &mt25q01_fixups,
 	}, {
 		.id = SNOR_ID(0x20, 0xbb, 0x21),
 		.name = "n25q00a",
-- 
2.34.1


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Re: [PATCH v3 0/5] mtd: spi-nor: introduce die erase

[Tudor Ambarus]

I made a typo on Fabio's email address. Now added correctly.

______________________________________________________
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Re: [PATCH v3 0/5] mtd: spi-nor: introduce die erase

[Fabio Estevam]

Hi Tudor,

On 25/11/2023 09:37, Tudor Ambarus wrote:
> I made a typo on Fabio's email address. Now added correctly.

It looks like the Subject of patch 3/5 is not complete:

[PATCH v3 3/5] mtd: spi-nor: micron-st: "

Feel free to add to this series:

Tested-by: Fabio Estevam <festevam@denx.de>

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Re: [PATCH v3 0/5] mtd: spi-nor: introduce die erase

[Tudor Ambarus]

On 11/25/23 17:29, Fabio Estevam wrote:
> Hi Tudor,

Hi!

> 
> On 25/11/2023 09:37, Tudor Ambarus wrote:
>> I made a typo on Fabio's email address. Now added correctly.
> 
> It looks like the Subject of patch 3/5 is not complete:
> 
> [PATCH v3 3/5] mtd: spi-nor: micron-st: "
> 
> Feel free to add to this series:
> 
> Tested-by: Fabio Estevam <festevam@denx.de>


Thanks, will do. Would you please replicate the tests that I did in
patch 3/5 for mt25qu01q? You'll have to modify a bit the offsets for the
die and cross die tests.

Cheers,
ta

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Re: [PATCH v3 0/5] mtd: spi-nor: introduce die erase

[Fabio Estevam]

On 30/11/2023 07:42, Tudor Ambarus wrote:

> Thanks, will do. Would you please replicate the tests that I did in
> patch 3/5 for mt25qu01q? You'll have to modify a bit the offsets for 
> the
> die and cross die tests.


Here it goes.

Can this series be applied now?

:~# cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mt25qu01g

:~# cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
20bb21104400

:~# cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
st

:~# xxd -p  
/sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp
53464450060101ff00060110300000ff84000102800000ffffffffffffff
ffffffffffffffffffffffffffffffffffffe520fbffffffff3f29eb276b
273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e
03e1ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff
ffffffffffffffffffe7ffff21dcffff

:~# sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
e49dfee6eeb73c55e94c07a8c7d352dd7d8774b830a64ed1059ef6e7bc833668  
/sys/bus/spi/devices/spi0.0/spi-nor/sfdp

:~# cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
  1S-1S-1S
   opcode	0x13
   mode cycles	0
   dummy cycles	0
  1S-1S-2S
   opcode	0x3c
   mode cycles	1
   dummy cycles	7
  1S-2S-2S
   opcode	0xbc
   mode cycles	1
   dummy cycles	7
  2S-2S-2S
   opcode	0xbc
   mode cycles	1
   dummy cycles	7
  1S-1S-4S
   opcode	0x6c
   mode cycles	1
   dummy cycles	7
  1S-4S-4S
   opcode	0xec
   mode cycles	1
   dummy cycles	9
  4S-4S-4S
   opcode	0xec
   mode cycles	1
   dummy cycles	9

Supported page program modes by the flash
  1S-1S-1S
   opcode	0x12
  1S-1S-4S
   opcode	0x34
  1S-4S-4S
   opcode	0x3e

:~# cat /sys/kernel/debug/spi-nor/spi0.0/params
name		mt25qu01g
id		20 bb 21 10 44 00
size		128 MiB
write size	1
page size	256
address nbytes	4
flags		4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | SOFT_RESET

opcodes
  read		0x6c
   dummy cycles	8
  erase		0x21
  program	0x12
  8D extension	none

protocols
  read		1S-1S-4S
  write		1S-1S-1S
  register	1S-1S-1S

erase commands
  21 (4.00 KiB) [1]
  dc (64.0 KiB) [3]
  c4 (128 MiB)

sector map
  region (in hex)   | erase mask | flags
  ------------------+------------+----------
  00000000-07ffffff |     [ 123] |
root@mcde3000a:~#

:~# dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.1 MB, 2.0 MiB) copied, 0.0303915 s, 69.0 MB/s

:~# mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
:~# mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
:~# hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
:~# sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5  
spi_read
:~# mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash

:~# mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
:~# sha256sum spi*
d5c15629e1fa019941cb820eff6ffd2a9008b5796bb23a67c351f42af48ce180  
spi_read
d5c15629e1fa019941cb820eff6ffd2a9008b5796bb23a67c351f42af48ce180  
spi_test
:~# mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash

:~# mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
:~# sha256sum spi*
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5  
spi_read
d5c15629e1fa019941cb820eff6ffd2a9008b5796bb23a67c351f42af48ce180  
spi_test
:~# mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 134217728 (128M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0


real	0m0.005s
user	0m0.001s
sys	0m0.005s
:~# time mtd_debug erase /dev/mtd0 0 134217728
Erased 134217728 bytes from address 0x00000000 in flash

real	0m1.768s
user	0m0.001s
sys	0m1.609s
:~# echo "ta writes something into the first die" > firstdie
:~# echo "ta writes something into the second die" > seconddie
:~# ls -al
total 4112
drwx------ 2 root root    4096 Dec  4 20:36 .
drwxr-xr-x 4 root root    4096 Mar  9  2018 ..
-rw-r--r-- 1 root root      39 Dec  4 20:36 firstdie
-rw-r--r-- 1 root root      40 Dec  4 20:36 seconddie
-rw-r--r-- 1 root root 2097152 Dec  4 20:35 spi_read
-rw-r--r-- 1 root root 2097152 Dec  4 20:32 spi_test
:~# mtd_debug write /dev/mtd0 0 39 firstdie
Copied 39 bytes from firstdie to address 0x00000000 in flash
:~# mtd_debug write /dev/mtd0 67108864 40 seconddie
Copied 40 bytes from seconddie to address 0x04000000 in flash
:~# mtd_debug read /dev/mtd0 0 134217728 read
Copied 134217728 bytes from address 0x00000000 in flash to read
:~# hexdump -C read
00000000  74 61 20 77 72 69 74 65  73 20 73 6f 6d 65 74 68  |ta writes 
someth|
00000010  69 6e 67 20 69 6e 74 6f  20 74 68 65 20 66 69 72  |ing into 
the fir|
00000020  73 74 20 64 69 65 0a ff  ff ff ff ff ff ff ff ff  |st 
die..........|
00000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  
|................|
*
04000000  74 61 20 77 72 69 74 65  73 20 73 6f 6d 65 74 68  |ta writes 
someth|
04000010  69 6e 67 20 69 6e 74 6f  20 74 68 65 20 73 65 63  |ing into 
the sec|
04000020  6f 6e 64 20 64 69 65 0a  ff ff ff ff ff ff ff ff  |ond 
die.........|
04000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  
|................|
*
08000000
:~# time mtd_debug erase /dev/mtd0 0 134217728
Erased 134217728 bytes from address 0x00000000 in flash

real	0m2.029s
user	0m0.001s
sys	0m1.853s

:~# echo "ta writes a something crossing the dice" > cross-dice
:~# mtd_debug write /dev/mtd0 67108857 40 cross-dice
Copied 40 bytes from cross-dice to address 0x03fffff9 in flash

:~# mtd_debug read /dev/mtd0 0 134217728 read
Copied 134217728 bytes from address 0x00000000 in flash to read
:~# hexdump -C read
00000000  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  
|................|
*
03fffff0  ff ff ff ff ff ff ff ff  ff 74 61 20 77 72 69 74  |.........ta 
writ|
04000000  65 73 20 61 20 73 6f 6d  65 74 68 69 6e 67 20 63  |es a 
something c|
04000010  72 6f 73 73 69 6e 67 20  74 68 65 20 64 69 63 65  |rossing the 
dice|
04000020  0a ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  
|................|
04000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  
|................|
*
08000000
:~# mtd_debug read /dev/mtd0 67108857 40 read
Copied 40 bytes from address 0x03fffff9 in flash to read
:~# hexdump -C read
00000000  74 61 20 77 72 69 74 65  73 20 61 20 73 6f 6d 65  |ta writes a 
some|
00000010  74 68 69 6e 67 20 63 72  6f 73 73 69 6e 67 20 74  |thing 
crossing t|
00000020  68 65 20 64 69 63 65 0a                           |he dice.|
00000028
:~#

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Re: [PATCH v3 0/5] mtd: spi-nor: introduce die erase

[Tudor Ambarus]

On 04.12.2023 22:59, Fabio Estevam wrote:
> 
>> Thanks, will do. Would you please replicate the tests that I did in
>> patch 3/5 for mt25qu01q? You'll have to modify a bit the offsets for the
>> die and cross die tests.
> 
> 
> Here it goes.

Wonderful, thanks!

> 
> Can this series be applied now?

Yes. Michael, any objections?

Thanks,
ta

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Re: [PATCH v3 0/5] mtd: spi-nor: introduce die erase

[Tudor Ambarus]

On Sat, 25 Nov 2023 14:35:24 +0200, Tudor Ambarus wrote:
> changes in v3:
> - fix code, thanks to Fabio's testing
> - found a n25q00 and tested on my side too
> - fixed micron's die erase support
> 
> Add support for die erase.
> JESD216 mentions die erase, but does not provide an opcode for it.
> Check BFPT dword 11, bits 30:24, "Chip Erase, Typical time", it says:
> 
> [...]

Applied to git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git,
spi-nor/next branch. Thanks!

[1/5] mtd: spi-nor: add erase die (chip) capability
      https://git.kernel.org/mtd/c/9641423174d0
[2/5] mtd: spi-nor: spansion: enable die erase for multi die flashes
      https://git.kernel.org/mtd/c/461d0babb544
[3/5] mtd: spi-nor: micron-st: enable die erase for multi die flashes
      https://git.kernel.org/mtd/c/53919a968b43
[4/5] mtd: spi-nor: remove NO_CHIP_ERASE flag
      https://git.kernel.org/mtd/c/06de1257aae7
[5/5] mtd: spi-nor: micron-st: Add support for mt25qu01g
      https://git.kernel.org/mtd/c/c692ba6de1c5

Cheers,
-- 
Tudor Ambarus <tudor.ambarus@linaro.org>

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