From: <Tudor.Ambarus@microchip.com>
To: <p.yadav@ti.com>
Cc: <michael@walle.cc>, <vigneshr@ti.com>,
<miquel.raynal@bootlin.com>, <richard@nod.at>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<Nicolas.Ferre@microchip.com>, <zhengxunli@mxic.com.tw>,
<jaimeliao@mxic.com.tw>
Subject: Re: [PATCH v2 2/2] mtd: spi-nor: macronix: Add support for mx66lm1g45g
Date: Mon, 20 Dec 2021 11:05:47 +0000 [thread overview]
Message-ID: <dac4db71-1f4b-13df-da9b-bedc2c0c2d4a@microchip.com> (raw)
In-Reply-To: <20211220101639.ycdz4twnhhp5bvlj@ti.com>
On 12/20/21 12:16 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Tudor,
>
> On 17/12/21 12:38PM, Tudor.Ambarus@microchip.com wrote:
>> On 12/17/21 1:38 PM, Pratyush Yadav wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 09/12/21 09:04PM, Tudor Ambarus wrote:
>>>> mx66lm1g45g supports just 1-1-1, 8-8-8 and 8d-8d-8d modes. There are
>>>> versions of mx66lm1g45g which do not support SFDP, thus use
>>>> SPI_NOR_SKIP_SFDP. The RDID command issued through the octal peripheral
>>>> interface outputs data always in STR mode for whatever reason. Since
>>>
>>> Huh! I hope this is a mistake from the chip designers, because if it
>>> isn't they need a stern talking-to ;-)
>>>
>>>> 8d-8d-8s is not common, avoid reading the ID when enabling the octal dtr
>>>> mode. Instead, read back the CR2 to check if the switch was successful.
>>>> Tested in 1-1-1 and 8d-8d-8d modes using sama7g5 QSPI IP.
>>>
>>> Datasheet?
>>
>> MX66LM1G45G datasheet:
>> https://www.macronix.com/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf
>
> Thanks.
>
> I see that the RDID waveform holds each byte of the ID for a whole clock
> cycle. So you would read ab ab cd cd ef ef. I've seen this before
> somewhere, and sure enough, digging through my inbox I've found this
> patch [0]. In this read ID is performed but only alternate bytes are
> compared since they are repeated. I think you should do the same. I feel
> like reading/comparing 3 bytes is more "robust".
I didn't want to do the 8D-8D-8S readID because I'm not sure if macronix
generalizes 8D-8D-8S for all its octal flashes. Since 8D-8D-8S is odd,
I felt that reading CR2 is safer. But maybe we'll follow the read CR2
approach when the need arises, so I'll follow Zhengxun's proposal.
>
> BTW, this patch series also adds support for mx66lm1g45g. You might want
> to use this as reference.
>
> [0] https://lore.kernel.org/all/20210812150135.4005-2-zhengxunli.mxic@gmail.com/
>
Right. I will rework it's 01/15 patch and keep Zhengxunli as author, I assume
Zhengxunli sent the proposal before me.
ta
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next prev parent reply other threads:[~2021-12-20 11:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-09 19:04 [PATCH v2 1/2] mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag Tudor Ambarus
2021-12-09 19:04 ` [PATCH v2 2/2] mtd: spi-nor: macronix: Add support for mx66lm1g45g Tudor Ambarus
2021-12-17 11:38 ` Pratyush Yadav
2021-12-17 12:38 ` Tudor.Ambarus
2021-12-20 10:16 ` Pratyush Yadav
2021-12-20 11:05 ` Tudor.Ambarus [this message]
2021-12-17 10:42 ` [PATCH v2 1/2] mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag Pratyush Yadav
-- strict thread matches above, loose matches on Subject: below --
2021-12-17 13:41 Tudor Ambarus
2021-12-17 13:41 ` [PATCH v2 2/2] mtd: spi-nor: macronix: Add support for mx66lm1g45g Tudor Ambarus
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