From: Michael Walle <michael@walle.cc>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Jaime Liao <jaimeliao.tw@gmail.com>,
linux-mtd@lists.infradead.org, pratyush@kernel.org,
miquel.raynal@bootlin.com, leoyu@mxic.com.tw
Subject: Re: [PATCH v1 0/2] Add octal DTR support for Macronix flash
Date: Tue, 25 Jul 2023 10:28:07 +0200 [thread overview]
Message-ID: <e2058fb379fb0b0d80b2b8c0d07c23ce@walle.cc> (raw)
In-Reply-To: <15276c56-011c-1b55-d905-d0fbb822c4ef@linaro.org>
Am 2023-07-25 10:01, schrieb Tudor Ambarus:
> On 7/25/23 03:23, Jaime Liao wrote:
>> From: JaimeLiao <jaimeliao.tw@gmail.com>
>>
>> This series add method for Macronix Octal DTR Eable/Disable
>> and add Macronix Octal flash support.
>
> Do all these flashes swap the bytes in octal DTR mode? If yes,
> you should add the infrastructure so that controllers can swap
> the bytes back, otherwise you'll break bootloaders which work
> in 1-1-1 mode, and breaking the boot chain is unacceptable.
It might also be the SPI controller. Was the zynq SPI controller
used before with octal flashes?
-michael
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next prev parent reply other threads:[~2023-07-25 8:28 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-25 2:23 [PATCH v1 0/2] Add octal DTR support for Macronix flash Jaime Liao
2023-07-25 2:23 ` [PATCH v1 1/2] mtd: spi-nor: add Octal " Jaime Liao
2023-07-25 7:16 ` Michael Walle
2023-07-25 9:05 ` liao jaime
2023-07-25 9:28 ` Michael Walle
2023-07-25 9:49 ` liao jaime
2023-07-25 2:23 ` [PATCH v1 2/2] mtd: spi-nor: add support for Macronix Octal flash Jaime Liao
2023-07-25 7:40 ` Michael Walle
2023-07-25 9:21 ` liao jaime
2023-07-25 9:39 ` Michael Walle
2023-07-25 9:55 ` liao jaime
2023-07-25 8:01 ` [PATCH v1 0/2] Add octal DTR support for Macronix flash Tudor Ambarus
2023-07-25 8:28 ` Michael Walle [this message]
2023-07-25 8:47 ` Tudor Ambarus
2023-07-25 9:25 ` liao jaime
2023-07-25 10:50 ` Tudor Ambarus
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